PIC16F913-E/ML Microchip Technology, PIC16F913-E/ML Datasheet - Page 141

• Manufacturer Part Number: PIC16F913-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F913-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SSP, I2C, AUSART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2
The following bits are used to configure the AUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
The LCD SEG8 and SEG9 functions must be disabled
by clearing the SE8 and SE9 bits of the LCDSE1
register, if the RX/DT and TX/CK pins are shared with
the LCD peripheral.
9.3.2.1
The operation of the Synchronous Master and Slave
modes are identical (see Section 9.3.1.2 “Synchronous
Master Transmission”), except in the case of the Sleep
mode.
TABLE 9-8:
© 2007 Microchip Technology Inc.
INTCON
LCDCON
LCDSE1
PIE1
PIR1
RCSTA
SSPCON
TRISC
TXREG
TXSTA
Legend:
Name
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
SYNCHRONOUS SLAVE MODE
AUSART Transmit Data Register
TRISC7
LCDEN
WCOL
SPEN
CSRC
AUSART Synchronous Slave
Transmit
SE15
EEIE
Bit 7
EEIF
GIE
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TRISC6
SSPOV
SLPEN
SE14
ADIE
ADIF
Bit 6
PEIE
RX9
TX9
TRISC5
SSPEN
WERR
SREN
TXEN
SE13
RCIE
RCIF
Bit 5
T0IE
VLCDEN
TRISC4
CREN
SYNC
SE12
Bit 4
INTE
TXIE
TXIF
CKP
PIC16F913/914/916/917/946
TRISC3
ADDEN
SSPM3
SSPIE
SSPIF
SE11
RBIE
Bit 3
CS1
—
CCP1IE
CCP1IF
TRISC2
SSPM2
BRGH
FERR
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
9.3.2.2
1.
2.
3.
4.
5.
6.
7.
8.
SE10
Bit 2
T0IF
CS0
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR2IE
TMR2IF
TRISC1
LMUX1
SSPM1
OERR
TRMT
Bit 1
INTF
SE9
transmission
Synchronous Slave Transmission
Set-up:
TMR1IE
TMR1IF
TRISC0
LMUX0
SSPM0
RX9D
TX9D
Bit 0
RBIF
SE8
by
0000 000x
0001 0011
0000 0000
0000 0000
0000 0000
0000 000X
0000 0000
1111 1111
0000 0000
0000 -010
POR, BOR
Value on
writing
DS41250F-page 139
the
0000 000x
0001 0011
0000 0000
0000 0000
0000 0000
0000 000X
0000 0000
1111 1111
0000 0000
0000 -010
Value on
all other
Resets
Least