PIC16F913-E/ML Microchip Technology, PIC16F913-E/ML Datasheet - Page 203

• Manufacturer Part Number: PIC16F913-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F913-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SSP, I2C, AUSART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
Normal
transmit/receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the SSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
14.9
A Reset disables the SSP module and terminates the
current transfer.
TABLE 14-2:
© 2007 Microchip Technology Inc.
Name
INTCON
LCDCON
LCDSE0
LCDSE1
PIE1
PIR1
RCSTA
SSPBUF
SSPCON
SSPSTAT
TRISA
TRISC
Legend:
Sleep Operation
Effects of a Reset
mode,
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
Synchronous Serial Port Receive Buffer/Transmit Register
TRISA7
TRISC7
LCDEN
WCOL
SPEN
SE15
EEIE
EEIF
Bit 7
SMP
SE7
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
the
SSPOV
TRISA6
TRISC6
SLPEN
SE14
PEIE
ADIE
ADIF
Bit 6
CKE
SE6
RX9
module
TRISC5
TRISA5
SSPEN
WERR
SREN
SE13
RCIE
RCIF
Bit 5
T0IE
SE5
D/A
will
continue
VLCDEN
TRISC4
TRISA4
CREN
SE12
INTE
TXIE
TXIF
Bit 4
CKP
SE4
P
PIC16F913/914/916/917/946
TRISC3
to
ADDEN
SSPM3
TRISA3
SSPIE
SSPIF
RBIE
SE11
Bit 3
CS1
SE3
S
CCP1IE
CCP1IF
TRISC2
SSPM2
TRISA2
FERR
14.10 Bus Mode Compatibility
Table 14-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 14-1:
There is also a SMP bit which controls when the data is
sampled.
SE10
Bit 2
T0IF
CS0
SE2
R/W
Standard SPI Mode
Terminology
TMR2IE
TMR2IF
TRISA1
TRISC1
LMUX1
SSPM1
OERR
0, 0
0, 1
1, 0
1, 1
Bit 1
INTF
SE1
SE9
UA
SPI BUS MODES
TMR1IE
TMR1IF
TRISA0
TRISC0
LMUX0
SSPM0
RX9D
Bit 0
RBIF
SE0
SE8
BF
0000 000x
0001 0011
0000 0000
0000 0000
0000 0000
0000 0000
0000 000x
xxxx xxxx
0000 0000
0000 0000
1111 1111
1111 1111
POR, BOR
CKP
Control Bits State
Value on
0
0
1
1
DS41250F-page 201
other Resets
Value on all
0000 000x
0001 0011
0000 0000
0000 0000
0000 0000
0000 0000
0000 000x
uuuu uuuu
0000 0000
0000 0000
1111 1111
1111 1111
CKE
1
0
1
0