PIC16F916-E/SO Microchip Technology, PIC16F916-E/SO Datasheet - Page 174
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PIC16F916-E/SO
Manufacturer Part Number
PIC16F916-E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F913-ISS.pdf
(330 pages)
3.PIC16F913-ISS.pdf
(8 pages)
4.PIC16F913-ISS.pdf
(34 pages)
Specifications of PIC16F916-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
352 B
Interface Type
SSP, I2C, AUSART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Data Rom Size
256 B
Height
2.31 mm
Length
17.87 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F913-ISS PDF datasheet #2
- PIC16F913-ISS PDF datasheet #3
- PIC16F913-ISS PDF datasheet #4
- Current page: 174 of 330
- Download datasheet (7Mb)
PIC16F913/914/916/917/946
11.1
To setup the PLVD for operation, the following steps
must be taken:
• Enable the module by setting the LVDEN bit of the
• Configure the trip point by setting the LVDL<2:0>
• Wait for the reference voltage to become stable.
• Clear the LVDIF bit of the PIR2 register.
The LVDIF bit will be set when V
PLVD trip point. The LVDIF bit remains set until cleared
by software. Refer to Figure 11-2.
11.2
The PLVD trip point is selectable from one of eight
voltage levels. The LVDL bits of the LVDCON register
select the trip point. Refer to Register 11-1 for the
available PLVD trip points.
11.3
When V
edge detector will set the LVDIF bit. See Figure 11-2.
An interrupt will be generated if the following bits are
also set:
• GIE and PEIE bits of the INTCON register
• LVDIE bit of the PIE2 register
The LVDIF bit must be cleared by software. An interrupt
can be generated from a simulated PLVD event when
the LVDIF bit is set by software.
DS41250F-page 172
LVDCON register.
bits of the LVDCON register.
Refer to Section 11.4 “Stable Reference
Indication”.
DD
PLVD Operation
Programmable Trip Point
Interrupt on Falling V
falls below the PLVD trip point, the falling
DD
DD
falls below the
11.4
When the PLVD module is enabled, the reference volt-
age must be allowed to stabilize before the PLVD will
provide a valid result. Refer to Section 19.0 “Electri-
cal Specifications”, Table 19-13, for the stabilization
time.
When the HFINTOSC is running, the IRVST bit of the
LVDCON register indicates the stability of the voltage
reference. The voltage reference is stable when the
IRVST bit is set.
11.5
To wake from Sleep, set the LVDIE bit of the PIE2
register and the PEIE bit of the INTCON register. When
the LVDIE and PEIE bits are set, the device will wake
from Sleep and execute the next instruction. If the GIE
bit is also set, the program will call the Interrupt Service
Routine upon completion of the first instruction after
waking from Sleep.
Stable Reference Indication
Operation During Sleep
© 2007 Microchip Technology Inc.
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