PIC16F916-E/SO Microchip Technology, PIC16F916-E/SO Datasheet - Page 192
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F916-E/SO
Manufacturer Part Number
PIC16F916-E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F913-ISS.pdf
(330 pages)
3.PIC16F913-ISS.pdf
(8 pages)
4.PIC16F913-ISS.pdf
(34 pages)
Specifications of PIC16F916-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
352 B
Interface Type
SSP, I2C, AUSART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Data Rom Size
256 B
Height
2.31 mm
Length
17.87 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F913-ISS PDF datasheet #2
- PIC16F913-ISS PDF datasheet #3
- PIC16F913-ISS PDF datasheet #4
- Current page: 192 of 330
- Download datasheet (7Mb)
PIC16F913/914/916/917/946
13.1.2
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD
control bit, and then set control bit RD of the EECON1
register. The data is available in the very next cycle, in
the EEDATL register; therefore, it can be read in the
next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).
EXAMPLE 13-1:
13.1.3
To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the sequence described below
is not followed exactly (write 55h to EECON2, write AAh
to EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
DS41250F-page 190
BANKSEL EEADRL
MOVF
MOVWF
BANKSEL EECON1
BCF
BSF
BANKSEL EEDATL
MOVF
READING THE DATA EEPROM
MEMORY
WRITING TO THE DATA EEPROM
MEMORY
DATA_EE_ADDR,W ;Data Memory
EEADRL
EECON1,EEPGD
EECON1,RD
EEDATL,W
DATA EEPROM READ
;
;Address to read
;
;Point to Data
;memory
;EE Read
;
;W = EEPROM Data
The steps to write to EEPROM data memory are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. At the completion of the write cycle, the WR bit
EXAMPLE 13-2:
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
Write the address to EEADRL. Make sure that
the address is not larger than the memory size
of the device.
Write the 8-bit data value to be programmed in
the EEDATL register.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the WREN bit to enable program operations.
Disable interrupts (if enabled).
Execute the special five instruction sequence:
Enable interrupts (if using interrupts).
Clear the WREN bit to disable program
operations.
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
• Write 55h to EECON2 in two steps (first to W,
• Write AAh to EECON2 in two steps (first to
• Set the WR bit
BANKSEL EECON1
BTFSC
GOTO
BANKSEL EEADRL
MOVF
MOVWF
MOVF
MOVWF
BANKSEL EECON1
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
then to EECON2)
W, then to EECON2)
EECON1,WR
$-1
DATA_EE_ADDR,W ;Data Memory
EEADRL
DATA_EE_DATA,W ;Data Memory Value
EEDATL
EECON1,EEPGD
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
EECON1,WREN
DATA EEPROM WRITE
© 2007 Microchip Technology Inc.
;
;Wait for write
;to complete
;
;Address to write
;to write
;
;Point to DATA
;memory
;Enable writes
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit to
;begin write
;Enable INTs.
;Disable writes
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