PIC16LF818-I/PTSL Microchip Technology, PIC16LF818-I/PTSL Datasheet - Page 23
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PIC16LF818-I/PTSL
Manufacturer Part Number
PIC16LF818-I/PTSL
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(176 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16LF818-I/PTSL
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- Current page: 23 of 176
- Download datasheet (4Mb)
2.2.2.6
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6:
2.2.2.7
The PIR2 register contains the flag bit for the EEPROM
write operation interrupt.
REGISTER 2-7:
2004 Microchip Technology Inc.
bit 7-5
bit 4
bit 3-0
bit 7-5
bit 4
bit 3-0
PIE2 Register
PIR2 Register
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)
bit 7
bit 7
Unimplemented: Read as ‘0’
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE write interrupt
0 = Disable EE write interrupt
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
Unimplemented: Read as ‘0’
EEIF: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE write interrupt
0 = Disable EE write interrupt
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
U-0
U-0
—
—
U-0
U-0
—
—
U-0
U-0
—
—
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
EEIF
EEIE
.
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
PIC16F818/819
U-0
U-0
—
—
x = Bit is unknown
x = Bit is unknown
U-0
U-0
—
—
DS39598E-page 21
U-0
U-0
—
—
bit 0
bit 0
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