PIC16LF818-I/PTSL Microchip Technology, PIC16LF818-I/PTSL Datasheet - Page 34
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PIC16LF818-I/PTSL
Manufacturer Part Number
PIC16LF818-I/PTSL
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(176 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16LF818-I/PTSL
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- Current page: 34 of 176
- Download datasheet (4Mb)
PIC16F818/819
3.8
There are conditions when the device should not write
to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
TABLE 3-1:
DS39598E-page 32
10Ch
10Dh
10Eh
10Fh
18Ch
18Dh
0Dh
8Dh
Legend:
Address
Protection Against Spurious Write
EEDATA EEPROM/Flash Data Register Low Byte
EEADR
EEDATH
EEADRH
EECON1 EEPGD
EECON2 EEPROM Control Register 2 (not a physical register)
PIR2
PIE2
Name
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM or Flash program memory.
Timer
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND
FLASH PROGRAM MEMORIES
EEPROM/Flash Address Register Low Byte
(72 ms
Bit 7
—
—
—
—
duration)
Bit 6
—
—
—
—
—
EEPROM/Flash Data Register High Byte
Bit 5
—
—
—
—
prevents
FREE
EEIE
Bit 4
EEIF
—
an
WRERR
Bit 3
—
—
—
information). External access to the memory is also
disabled.
3.9
When the data EEPROM is code-protected, the micro-
controller can read and write to the EEPROM normally.
However, all external access to the EEPROM is
disabled. External write access to the program memory
is also disabled.
When program memory is code-protected, the micro-
controller can read and write to program memory
normally as well as execute instructions. Writes by the
device may be selectively inhibited to regions of
the memory depending on the setting of bits,
WRT1:WRT0,
Section 12.1 “Configuration Bits” for additional
EEPROM/Flash Address
Register High Byte
WREN
Bit 2
—
—
Operation During Code-Protect
Bit 1
WR
—
—
of
the
Bit 0
RD
—
—
2004 Microchip Technology Inc.
Configuration
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
---- -xxx ---- -uuu
x--x x000 x--x q000
---- ---- ---- ----
---0 ---- ---0 ----
---0 ---- ---0 ----
Power-on
Value on
Reset
Word
Value on
all other
Resets
(see
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