PIC17C756A-33/PT Microchip Technology, PIC17C756A-33/PT Datasheet - Page 123
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,QFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC17C756A-33/PT
Manufacturer Part Number
PIC17C756A-33/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,QFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-TFQFP
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
12 bit
Data Rom Size
902 B
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-33/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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14.2
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip dedicated 8-bit baud rate genera-
tor can be used to derive standard baud rate frequen-
cies from the oscillator. The USART’s transmitter and
receiver are functionally independent but use the same
data format and baud rate. The baud rate generator
produces a clock x64 of the bit shift rate. Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
The Asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing components:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
14.2.1
The USART transmitter block diagram is shown in
Figure 14-1. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded until
the STOP bit has been transmitted from the previous
load. As soon as the STOP bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one T
is empty and an interrupt bit, TXIF, is set. This interrupt
can be enabled/disabled by setting/clearing the TXIE bit.
TXIF will be set, regardless of TXIE and cannot be reset
in software. It will reset only when new data is loaded into
TXREG. While TXIF indicates the status of the TXREG,
the TRMT (TXSTA<1>) bit shows the status of the TSR.
FIGURE 14-3:
2000 Microchip Technology Inc.
Write to TXREG
CY
(TX/CK pin)
BRG Output
(Shift Clock)
at the end of the current BRG cycle), the TXREG
TRMT bit
USART Asynchronous Mode
TXIF bit
USART ASYNCHRONOUS
TRANSMITTER
TX
ASYNCHRONOUS MASTER TRANSMISSION
Word 1
Transmit Shift Reg
Word 1
START Bit
Bit 0
Bit 1
Word 1
TRMT is a read only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user has
to poll this bit in order to determine if the TSR is empty.
Transmission
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 14-3). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally,
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR, resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 14-4). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the TX/CK
pin will revert to hi-impedance.
In
TX9 (TXSTA<6>) bit should be set and the ninth bit
value should be written to TX9D (TXSTA<0>). The
ninth bit value must be written before writing the 8-bit
data to the TXREG. This is because a data write to
TXREG can result in an immediate transfer of the data
to the TSR (if the TSR is empty).
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Note:
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Load data to the TXREG register.
Enable the transmission by setting TXEN (starts
transmission).
order
The TSR is not mapped in data memory,
so it is not available to the user.
to
is
select
Bit 7/8
enabled
PIC17C7XX
STOP Bit
9-bit
by
transmission,
DS30289B-page 123
setting
the
the
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