PIC17C756A-33/PT Microchip Technology, PIC17C756A-33/PT Datasheet - Page 210
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,QFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC17C756A-33/PT
Manufacturer Part Number
PIC17C756A-33/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,QFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-TFQFP
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
12 bit
Data Rom Size
902 B
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-33/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C7XX
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
DS30289B-page 210
Before Instruction
After Instruction
operation
Decode
PC
W
If REG
PC
If REG
PC
Q1
Q1
No
register ’f’
operation
Compare f with WREG,
skip if f < WREG
[ label ] CPFSLT
0
(f) – WREG),
skip if (f) < (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location ’f’ to the contents of WREG by
performing an unsigned subtraction.
If the contents of ’f’ are less than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
1
1 (2)
HERE
NLESS
LESS
Read
0011
Q2
Q2
No
=
=
<
=
f
=
255
Address (HERE)
?
WREG;
Address (LESS)
WREG;
Address (NLESS)
CPFSLT REG
:
:
0000
operation
Process
Data
Q3
Q3
No
ffff
f
operation
operation
Q4
Q4
No
No
ffff
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
REG1
C
DC
WREG
REG1
C
DC
Q1
=
=
=
=
=
=
=
=
register ’f’
Decimal Adjust WREG Register
[label] DAW
0
s
If [ [WREG<7:4> > 9].OR.[C = 1] ].AND.
[WREG<3:0> > 9]
then
WREG<7:4> + 7
If [WREG<7:4> > 9].OR.[C = 1]
then
WREG<7:4> + 6
else
WREG<7:4>
If [WREG<3:0> > 9].OR.[DC = 1]
then
WREG<3:0> + 6
else
WREG<3:0>
C
DAW adjusts the eight-bit value in
WREG, resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0:
s = 1:
1
1
DAW
Read
0010
Q2
0xA5
??
0
0
0x05
0x05
1
0
f
[0,1]
2000 Microchip Technology Inc.
255
REG1, 0
Result is placed in Data
memory location ’f’ and
Result is placed in Data
memory location ’f’.
WREG.
111s
Process
f<7:4>, s<7:4>;
f<3:0>, s<3:0>
Data
Q3
f,s
f<7:4>, s<7:4>;
f<7:4>, s<7:4>;
f<3:0>, s<3:0>;
ffff
register ’f’
and other
specified
register
Write
Q4
ffff
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