PIC18F24J10T-I/SS Microchip Technology, PIC18F24J10T-I/SS Datasheet - Page 188
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PIC18F24J10T-I/SS
Manufacturer Part Number
PIC18F24J10T-I/SS
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
Specifications of PIC18F24J10T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F24J10T-I/SSTR
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- Current page: 188 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
FIGURE 16-24:
16.4.14
While in Sleep mode, the I
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
16.4.15
A Reset disables the MSSP module and terminates the
current transfer.
16.4.16
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I
be taken when the P bit (SSPxSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLxIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
DS39682E-page 186
SLEEP OPERATION
EFFECTS OF A RESET
MULTI-MASTER MODE
SCLx
SDAx
Note: T
Write to SSPxCON2,
Falling edge of
9th clock
BRG
STOP CONDITION RECEIVE OR TRANSMIT MODE
= one Baud Rate Generator period.
ACK
set PEN
2
C module can receive
T
T
BRG
BRG
SDAx asserted low before rising edge of clock
to set up Stop condition
2
C bus may
T
SCLx brought high after T
BRG
P
SCLx = 1 for T
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
T
BRG
condition is aborted, the SDAx and SCLx lines are deas-
collision Interrupt Service Routine, and if the I
16.4.17
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high, and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx
pin = 0, then a bus collision has taken place. The
master will set the Bus Collision Interrupt Flag, BCLxIF
and reset the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the I
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
serted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus
free, the user can resume communication by asserting a
Start condition.
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I
be taken when the P bit is set in the SSPxSTAT register,
or the bus is Idle and the S and P bits are cleared.
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
BRG
BRG
, followed by SDAx = 1 for T
MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
2
C port to its Idle state (Figure 16-25).
© 2009 Microchip Technology Inc.
BRG
2
C bus can
2
C bus is
2
C
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