PIC18F24J10T-I/SS Microchip Technology, PIC18F24J10T-I/SS Datasheet - Page 242
PIC18F24J10T-I/SS
Manufacturer Part Number
PIC18F24J10T-I/SS
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
Specifications of PIC18F24J10T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F24J10T-I/SSTR
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- Current page: 242 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
REGISTER 21-5:
REGISTER 21-6:
DS39682E-page 240
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-0
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-1
bit 0
Note 1:
—
U-0
U-0
—
(1)
The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘1’
CCP2MX: CCP2 MUX bit
1 = CCP2 is multiplexed with RC1
0 = CCP2 is multiplexed with RB3
—
U-0
U-0
—
(1)
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
WO = Write Once bit
WO = Write Once bit
—
U-0
U-0
—
(1)
(1)
—
U-0
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
© 2009 Microchip Technology Inc.
‘0’ = Bit is cleared
‘0’ = Bit is cleared
U-0
U-0
—
—
CCP2MX
R/WO-1
U-0
—
bit 0
bit 0
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