PIC18F448-I/L Microchip Technology, PIC18F448-I/L Datasheet - Page 229

• Manufacturer Part Number: PIC18F448-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F448-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCCDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F448I/L

19.3.5
This mode will allow internal transmission of messages
from the transmit buffers to the receive buffers without
actually transmitting messages on the CAN bus. This
mode can be used in system development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself, just as if they
were coming from another node. The Loopback mode
is a silent mode, meaning no messages will be trans-
mitted while in this state, including error flags or
Acknowledge signals. The TXCAN pin will revert to port
I/O while the device is in this mode. The filters and
masks can be used to allow only particular messages
to be loaded into the receive registers. The masks can
be set to all zeros to provide a mode that accepts all
messages. The Loopback mode is activated by setting
the mode request bits in the CANCON register.
19.3.6
The module can be set to ignore all errors and receive
all message. The Error Recognition mode is activated
by setting the RXM<1:0> bits in the RXBnCON
registers to ‘11’. In this mode, all messages, valid or
invalid, are received and copied to the receive buffer.
19.4
19.4.1
The PIC18FXX8 implements three transmit buffers
(Figure 19-2). Each of these buffers occupies 14 bytes
of SRAM and are mapped into the device memory
map.
For the MCU to have write access to the message
buffer, the TXREQ bit must be clear, indicating that the
message buffer is clear of any pending message to be
transmitted. At a minimum, the TXBnSIDH, TXBnSIDL
and TXBnDLC registers must be loaded. If data bytes
are present in the message, the TXBnDm registers
must also be loaded. If the message is to use extended
identifiers, the TXBnEIDm registers must also be
loaded and the EXIDE bit set.
Prior to sending the message, the MCU must initialize
the TXInE bit to enable or disable the generation of an
interrupt when the message is sent. The MCU must
also initialize the TXP priority bits (see Section 19.4.2
“Transmit Priority”).
© 2006 Microchip Technology Inc.
CAN Message Transmission
LOOPBACK MODE
ERROR RECOGNITION MODE
TRANSMIT BUFFERS
19.4.2
Transmit
PIC18FXX8 of the pending transmittable messages.
This is independent from and not related to any prioriti-
zation implicit in the message arbitration scheme built
into the CAN protocol. Prior to sending the SOF, the
priority of all buffers that are queued for transmission is
compared. The transmit buffer with the highest priority
will be sent first. If two buffers have the same priority
setting, the buffer with the highest buffer number will be
sent first. There are four levels of transmit priority. If
TXP bits for a particular message buffer are set to ‘11’,
that buffer has the highest possible priority. If TXP bits
for a particular message buffer are ‘00’, that buffer has
the lowest possible priority.
FIGURE 19-2:
Message
Request
Message
Control
Queue
priority
TRANSMIT PRIORITY
is
TRANSMIT BUFFER
BLOCK DIAGRAM
TXREQ
TXABT
TXLARB
TXERR
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXBUFF
a
PIC18FXX8
Transmit Byte Sequencer
prioritization
MESSAGE
MESSAGE
MESSAGE
DS41159E-page 227
TXB0
TXB1
TXB2
within
the