PIC18F44J10-I/ML Microchip Technology, PIC18F44J10-I/ML Datasheet - Page 193

Microcontroller

PIC18F44J10-I/ML

Manufacturer Part Number
PIC18F44J10-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F44J10-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
16.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 16-31:
FIGURE 16-32:
© 2009 Microchip Technology Inc.
After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDAx asserted low
Assert SDAx
T
T
BRG
BRG
T
BRG
T
BRG
PIC18F45J10 FAMILY
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the
SSPxADD<6:0> and counts down to 0. After the BRG
times out, SDAx is sampled. If SDAx is sampled low, a
bus collision has occurred. This is due to another
master attempting to drive a data ‘0’ (Figure 16-31). If
the SCLx pin is sampled low before SDAx is allowed to
float high, a bus collision occurs. This is another case
of another master attempting to drive a data ‘0’
(Figure 16-32).
Baud
SCLx goes low before SDAx goes high,
set BCLxIF
T
Rate
BRG
T
BRG
Generator
SDAx sampled
low after T
set BCLxIF
‘0’
‘0’
DS39682E-page 191
‘0’
‘0’
is
loaded
BRG
,
with

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