PIC18F44J10-I/ML Microchip Technology, PIC18F44J10-I/ML Datasheet - Page 92

• Manufacturer Part Number: PIC18F44J10-I/ML
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F44J10-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F45J10 FAMILY
9.3
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7:
DS39682E-page 90
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PSPIE
R/W-0
PIE Registers
(1)
This bit is not implemented on 28-pin devices and should be read as ‘0’.
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
CCP1IE: ECCP1/CCP1 Interrupt Enable bit
1 = Enables the ECCP1/CCP1 interrupt
0 = Disables the ECCP1/CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
ADIE
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
W = Writable bit
‘1’ = Bit is set
R/W-0
RCIE
R/W-0
TXIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSP1IE
R/W-0
(1)
CCP1IE
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
TMR2IE
R/W-0
TMR1IE
R/W-0
bit 0