PIC18F4520-E/PT Microchip Technology, PIC18F4520-E/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F4520-E/PT
• Description: 44 PIN, 32 KB ENH FLASH, 3804 RAM, 36 I/O, PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4520-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2420/2520/4420/4520
31. Module: MSSP
32. Module: MSSP (SPI Mode)
FIGURE 1:
DS80209H-page 10
In SPI mode, the Buffer Full flag (BF bit in the
SSPSTAT register), the Write Collision Detect bit
(WCOL bit in SSPCON1) and the Receive
Overflow Indicator bit (SSPOV in SSPCON1) are
not reset upon disabling the SPI module (by
clearing the SSPEN bit in the SSPCON1 register).
For example, if SSPBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
Date Codes that pertain to this issue:
All engineering and production devices.
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCK pulse may
occur on the first bit of the transmitted/received
data (Figure 1).
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit and then turn Timer2 back
on. Refer to Example 4 for sample code.
SDO
SCK
Write SSPBUF
bit 0 = 1 bit 1 = 0
SCK PULSE VARIATION
USING TIMER2/2
bit 2 = 1 . . . .
EXAMPLE 4:
33. Module: EUSART
LOOP BTFSSSSPSTAT, BF
received?
plete?)
RAM
Date Codes that pertain to this issue:
All engineering and production devices.
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREG, are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• TXREG is written to;
• the baud rate counter overflows (at the end of
• a Stop bit is being transmitted (shifted out of
Work around
If possible, do not use the module’s double-buffer
capability. Instead, load the TXREG register when
the TRMT bit (TXSTA<1>) is set, indicating the
TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, then load TXREG
immediately after TXIF is set or wait 1-bit time after
TXIF is set. Both solutions prevent writing TXREG
while a Stop bit is transmitted. Note that TXIF is set
at the beginning of the Stop bit transmission.
If transmission is intermittent, then do the
following:
Date Codes that pertain to this issue:
All engineering and production devices.
BRA
MOVF SSPBUF, W
MOVWF RXDATA
MOVF TXDATA, W
the bit period); and
TSR).
• Wait for the TRMT bit to be set before
• Alternatively, use a free timer resource to
loading TXREG.
time the baud period. Set up the timer to
overflow at the end of the Stop bit, then start
the timer when you load the TXREG. Do not
load the TXREG when timer is about to
overflow.
LOOP
AVOIDING THE INITIAL
SHORT SCK PULSE
© 2008 Microchip Technology Inc.
;(Xmit com-
;Save in user
;W = TXDATA
;Data
;No
;W = SSPBUF