PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet - Page 410

• Manufacturer Part Number: PIC18F64J90-I/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F85J90 FAMILY
RESET ............................................................................. 335
Reset .................................................................................. 51
Resets .............................................................................. 291
RETFIE ............................................................................ 336
DS39770C-page 410
CONFIG2H (Configuration 2 High) .......................... 295
CONFIG2L (Configuration 2 Low) ............................ 294
CONFIG3H (Configuration 3 High) .......................... 295
CVRCON (Comparator Voltage
DEVID1 (Device ID Register 1) ................................ 296
DEVID2 (Device ID Register 2) ................................ 296
EECON1 (EEPROM Control 1) .................................. 89
INTCON (Interrupt Control) ...................................... 101
INTCON2 (Interrupt Control 2) ................................. 102
INTCON3 (Interrupt Control 3) ................................. 103
IPR1 (Peripheral Interrupt Priority 1) ........................ 110
IPR2 (Peripheral Interrupt Priority 2) ........................ 111
IPR3 (Peripheral Interrupt Priority 3) ........................ 112
LCDCON (LCD Control) ........................................... 164
LCDDATAx (LCD Data) ........................................... 167
LCDPS (LCD Phase) ............................................... 165
LCDREG (LCD Voltage Regulator Control) ............. 169
LCDSEx (LCD Segment Enable) ............................. 166
OSCCON (Oscillator Control) .................................... 36
OSCTUNE (Oscillator Tuning) ................................... 37
PIE1 (Peripheral Interrupt Enable 1) ........................ 107
PIE2 (Peripheral Interrupt Enable 2) ........................ 108
PIE3 (Peripheral Interrupt Enable 3) ........................ 109
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 104
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 105
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 106
RCON (Reset Control) ....................................... 52, 113
RCSTA1 (EUSART Receive Status and Control) .... 237
RCSTA2 (AUSART Receive Status and Control) .... 259
SSPCON1 (MSSP Control 1, I
SSPCON1 (MSSP Control 1, SPI Mode) ................. 193
SSPCON2 (MSSP Control 2, I
SSPCON2 (MSSP Control 2, I
SSPSTAT (MSSP Status, I
SSPSTAT (MSSP Status, SPI Mode) ...................... 192
STATUS ..................................................................... 79
STKPTR (Stack Pointer) ............................................ 66
T0CON (Timer0 Control) .......................................... 137
T1CON (Timer1 Control) .......................................... 141
T2CON (Timer2 Control) .......................................... 147
T3CON (Timer3 Control) .......................................... 149
TXSTA1 (EUSART Transmit
TXSTA2 (AUSART Transmit
WDTCON (Watchdog Timer Control) ....................... 298
Brown-out Reset (BOR) ............................................. 51
MCLR Reset, During Power-Managed Modes ........... 51
MCLR Reset, Normal Operation ................................ 51
Power-on Reset (POR) .............................................. 51
RESET Instruction ..................................................... 51
Stack Full Reset ......................................................... 51
Stack Underflow Reset .............................................. 51
Watchdog Timer (WDT) Reset ................................... 51
Brown-out Reset (BOR) ........................................... 291
Oscillator Start-up Timer (OST) ............................... 291
Power-on Reset (POR) ............................................ 291
Power-up Timer (PWRT) ......................................... 291
Reference Control) ........................................... 287
Status and Control) .......................................... 236
Status and Control) .......................................... 258
2
C Mode) ....................... 201
2
2
2
C Mode) ................. 202
C Master Mode) ..... 203
C Slave Mode) ....... 204
RETLW ............................................................................ 336
RETURN .......................................................................... 337
Return Address Stack ........................................................ 65
Return Stack Pointer (STKPTR) ........................................ 66
Revision History ............................................................... 399
RLCF ............................................................................... 337
RLNCF ............................................................................. 338
RRCF ............................................................................... 338
RRNCF ............................................................................ 339
S
SCK ................................................................................. 191
SDI ................................................................................... 191
SDO ................................................................................. 191
SEC_IDLE Mode ............................................................... 48
SEC_RUN Mode ................................................................ 44
Serial Clock, SCK ............................................................ 191
Serial Data In (SDI) .......................................................... 191
Serial Data Out (SDO) ..................................................... 191
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 339
Slave Select (SS) ............................................................. 191
SLEEP ............................................................................. 340
Sleep
Software Simulator (MPLAB SIM) ................................... 357
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 291
SPI Mode (MSSP)
SS .................................................................................... 191
SSPOV ............................................................................ 225
SSPOV Status Flag ......................................................... 225
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 67
SUBFSR .......................................................................... 351
SUBFWB ......................................................................... 340
SUBLW ............................................................................ 341
SUBULNK ........................................................................ 351
SUBWF ............................................................................ 341
SUBWFB ......................................................................... 342
SWAPF ............................................................................ 342
T
Table Pointer Operations (table) ........................................ 90
Table Reads/Table Writes ................................................. 67
TBLRD ............................................................................. 343
TBLWT ............................................................................. 344
OSC1 and OSC2 Pin States ...................................... 42
Associated Registers ............................................... 199
Bus Mode Compatibility ........................................... 199
Effects of a Reset .................................................... 199
Enabling SPI I/O ...................................................... 195
Master Mode ............................................................ 196
Operation ................................................................. 194
Operation in Power-Managed Modes ...................... 199
Serial Clock .............................................................. 191
Serial Data In ........................................................... 191
Serial Data Out ........................................................ 191
Slave Mode .............................................................. 197
Slave Select ............................................................. 191
Slave Select Synchronization .................................. 197
SPI Clock ................................................................. 196
Typical Connection .................................................. 195
R/W Bit ............................................................ 205, 207
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