PIC18LF2221-I/ML Microchip Technology, PIC18LF2221-I/ML Datasheet - Page 145
![4 KB Flash, 512 RAM 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2221-I/ML
Manufacturer Part Number
PIC18LF2221-I/ML
Description
4 KB Flash, 512 RAM 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2221-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18LF2221-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- Current page: 145 of 402
- Download datasheet (7Mb)
16.0
PIC18F2221/2321/4221/4321 family devices all have
two CCP (Capture/Compare/PWM) modules. Each
module contains a 16-bit register which can operate as
a 16-bit Capture register, a 16-bit Compare register or
a PWM Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules
(CCP1 and CCP2) operate as described in this
chapter. In 40/44-pin devices, CCP1 is implemented
as an Enhanced CCP module with standard Capture
and Compare modes and Enhanced PWM modes.
The
Section 17.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
REGISTER 16-1:
© 2009 Microchip Technology Inc.
ECCP
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
implementation
CCPxCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES)
PIC18F2221/2321/4221/4321 FAMILY
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCxB<9:2>) of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
11xx = PWM mode
bit 7
Legend:
R = Readable bit
-n = Value at POR
U-0
—
(CCPxIF bit is set)
(CCPxIF bit is set)
CCP pin reflects I/O state)
CCPx match (CCPxIF bit is set)
is
U-0
discussed
—
DCxB1
R/W-0
W = Writable bit
‘1’ = Bit is set
in
DCxB0
R/W-0
The Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules.
Note: Throughout this section and Section 17.0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to
generically by the use of ‘x’ or ‘y’ in place
of the specific module number. Thus,
“CCPxCON” might refer to the control regis-
ter for CCP1, CCP2 or ECCP1. “CCPxCON”
is used throughout these sections to refer to
the module control register, regardless of
whether the CCP module is a standard or
Enhanced implementation.
CCPxM3
R/W-0
CCPxM2 CCPxM1 CCPxM0
R/W-0
x = Bit is unknown
R/W-0
DS39689F-page 145
R/W-0
bit 0
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