PIC18LF2221-I/ML Microchip Technology, PIC18LF2221-I/ML Datasheet - Page 158
![4 KB Flash, 512 RAM 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2221-I/ML
Manufacturer Part Number
PIC18LF2221-I/ML
Description
4 KB Flash, 512 RAM 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2221-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18LF2221-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- Current page: 158 of 402
- Download datasheet (7Mb)
signals.
PIC18F2221/2321/4221/4321 FAMILY
17.4.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 17-4). This
mode can be used for half-bridge applications, as shown
in Figure 17-5, or for full-bridge applications where four
power switches are being modulated with two PWM
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC<6:0>, sets the number of instruction cycles before
the output is driven active. If the value is greater than
the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 17.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 17-5:
DS39689F-page 158
HALF-BRIDGE MODE
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
PIC18F4X21
P1A
P1B
PIC18F4X21
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
FIGURE 17-4:
Note 1: At this time, the TMR2 register is equal to the
P1A
P1B
td = Dead-Band Delay
(2)
(2)
2: Output signals are shown as active-high.
Load
V+
V+
V-
V-
(1)
PR2 register.
Duty Cycle
td
Load
Period
td
HALF-BRIDGE PWM
OUTPUT
© 2009 Microchip Technology Inc.
FET
Driver
FET
Driver
+
V
-
+
V
-
(1)
Period
(1)
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