AS5130-ASST austriamicrosystems, AS5130-ASST Datasheet - Page 15
![IC ENCODER ROTORY 8-BIT 16-SSOP](/photos/19/50/195004/as5130-asst_sml.jpg)
AS5130-ASST
Manufacturer Part Number
AS5130-ASST
Description
IC ENCODER ROTORY 8-BIT 16-SSOP
Manufacturer
austriamicrosystems
Type
Linear, Rotary Encoder - Programmabler
Datasheet
1.AS5130-ASST.pdf
(41 pages)
Specifications of AS5130-ASST
Sensing Range
32mT ~ 75mT
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
24mA
Output Type
Analog, Ratiometric
Features
Programmable
Operating Temperature
-40°C ~ 125°C
Package / Case
16-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output (max)
-
Other names
AS5130-ASSTTR
AS5130
Data Sheet - D e t a i l e d D e s c r i p t i o n
7.2 Serial Synchronous Interface (SSI)
7.2.1 Commands of the SSI in Normal Mode
Table 9. SSI in Normal Mode
WD2COS / WD2SIN: xen_X disables Hall element X from the sensor array in the cosine or sine channel; xinv_X inverts the voltage output of Hall
element X in the channels.
RD2COS / RD2SIN: The Hall array configuration for cosine and sine channel can be read out by these commands, initial values are 0.
SET TEST CFG 1: gen_rst HI triggers a digital reset.
WRITE CONFIG: go2sleep HI activates the low power mode of the AS5130. The power consumption is significantly reduced. go2sleep LO
returns to normal operation mode. During low power mode, the lock bit in command 0 and command 1 is LO.
WRITE CUST: With “wlsb_x” the threshold level for generation of a WAKE pulse is set (only important in polling mode). The initial value is 4 LSB.
No value lower than 4 LSB can be set. The maximum value is 127 LSB.
“gain_x” sets the gain in the signal
HYST_RST: “setHyst” enables an additional hysteresis of the digital output signal. It is enabled by default. Only after 2 consecutive equal signals
the output is changed.
“rst_otp” forces the IC to read out the OTP in polling mode. This reset has to be performed after initial startup and every WAKE signal.
“rst_multi” resets the multi turn counter to 0.
READ CUST: With this command “wlsb_x” and “gain_x” can be read out.
RD_BOTH: Angle and multi turn counter value can be read out simultaneously by this command. Due to limited data size, the parity bit is not
available in this command.
STORE REF: This command stores the actual angle as reference angle in the storage registers (only important in polling mode). The output is
the stored angle (angle_stored), a flag, if the voltage at DVDD is OK (store_ok), a flag, if the supply voltage is OK (vdd_ok) and a check bit, if the
register was written.
RD_MULTI: Command for read out of multi turn register (multiturn) and AGC value (agc). “Lock” indicates a locked ADC and “parity” an even
parity checksum.
RD_ANGLE: Command for read out of angle value and AGC value (agc). “Lock” indicates a locked ADC and “parity” an even parity checksum.
www.austriamicrosystems.com/AS5130
23
22
21
20
19
18
17
16
#
7
6
5
4
3
2
1
0
WRITE CUST
READ CUST
STORE REF
RD_ANGLE
HYST_RST
RD_MULTI
SET TEST
RD_BOTH
WD2COS
RD2COS
reserved
WD2SIN
CONFIG
RD2SIN
WRITE
CFG1
cmd
--
10110
10101
10100
10011
10010
10001
10000
00111
00110
00101
00100
00011
00010
00001
00000
10111
bin
mode
write
write
write
write
write
write
write
write
read
read
read
read
read
read
read
read
rst_otp
go2sle
xen_7
xen_7
xen_7
store_
xen_7
lock
lock
15
ep
ok
vdd_ok reg_s
inv_7
inv_7
inv_7
inv_7
14
nc
xen_6 inv_6 xen_5
xen_6 inv_6 xen_5
xen_6 inv_6 xen_5
xen_6 inv_6 xen_5
rst_m
ulti
13
et
wlsb <6:0>
wlsb <6:0>
Multiturn <7:0>
12
nc
agc <5:0>
agc <5:0>
setHy
11
Revision 1.11
st
nc
gen_r
inv_5
inv_5
inv_5
inv_5
10
st
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
9
8
gain <2:0>
gain <2:0>
7
6
angle_stored <7:0>
Multiturn <7:0>
angle <7:0>
5
angle <7:0>
4
nc
3
nc
2
1
15 - 41
parity
parity
parity
parity
0