HMC5883L-TR Honeywell Microelectronics & Precision Sensors, HMC5883L-TR Datasheet - Page 15

• Manufacturer Part Number: HMC5883L-TR
• Description: IC COMPASS 3 AXIS I2C 16LCC SMD
• Manufacturer: Honeywell Microelectronics & Precision Sensors
• Series: HMCr
• Type: Compass - Three Axisr

Specifications of HMC5883L-TR

• Sensing Range: ±8G
• Voltage - Supply: 2.16 V ~ 3.6 V
• Current - Supply: 100µA
• Output Type: Differential Voltage
• Features: Compass - Three Axis
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 16-LCC
• Measuring Range: -8G To +8G
• Resolution: 5 MG
• Supply Voltage Range: 1.71V To 3.7V, 2.16V To 3.6V
• No. Of Axes: 3
• Sensor Case Style: LCC
• Ic Interface Type: I2C
• Supply Voltage Max: 3.6V
• No. Of Pins: 16
• Resoluti: 5 MG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 342-1082-2

HMC5883L
Data Output Register Operation
When one or more of the output registers are read, new data cannot be placed in any of the output data registers until all
six data output registers are read. This requirement also impacts DRDY and RDY, which cannot be cleared until new
data is placed in all the output registers.
Status Register
The status register is an 8-bit read-only register. This register is used to indicate device status. SR0 through SR7
indicate bit locations, with SR denoting the bits that are in the status register. SR7 denotes the first bit of the data stream.
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DZRA7
(0)
DZRB7
(0)
SR7
(0)
Location
SR7 to
SR2
SR1
SR0
DZRA6
(0)
DZRB6
(0)
SR6
(0)
Name
0
LOCK
RDY
Table 15: Data Output Z Registers A and B
Table 17: Status Register Bit Designations
SR5
(0)
DZRA5
(0)
DZRB5
(0)
Description
These bits are reserved. SR4 may be 0 or 1 depending on
internal activity. Disregard activity on this bit.
Data output register lock. This bit is set when this some but
not all for of the six data output registers have been read.
When this bit is set, the six data output registers are locked
and any new data will not be placed in these register until
one of three conditions are met: one, all six bytes have
been read or the mode changed, two, the mode is
changed, or three, the measurement configuration is
changed.
Ready Bit. Set when data is written to all six data registers.
Cleared when device initiates a write to the data output
registers and after one or more of the data output registers
are written to. When RDY bit is clear it shall remain cleared
for a 250 μs. DRDY pin can be used as an alternative to
the status register for monitoring the device for
measurement data.
Table 16: Status Register
SR4
(x)
DZRA4
(0)
DZRB4
(0)
SR3
(0)
DZRA3
(0)
DZRB3
(0)
SR2
(0)
DZRA2
(0)
DZRB2
(0)
SR1
LOCK (0)
DZRA1
(0)
DZRB1
(0)
SR0
RDY(0)
DZRA0
(0)
DZRB0
(0)
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