C500MP102EV3 Omron, C500MP102EV3 Datasheet - Page 117

• Manufacturer Part Number: C500MP102EV3
• Description: K-TYPE PC MEMORY RACK
• Manufacturer: Omron

Specifications of C500MP102EV3

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Data Shifting
5-12
5-12-1
106
Timing Example
Limitations
Present value
Start input 0002
Count input (1805)
Reset input (1804)
UP/DOWN selection (1806)
HR 000
Limits: 0001 to 0002
HR 001
Limits: 0002 to 0004
HR 015
Limits: 9980 to 9999
Data Shifting
SHIFT REGISTER – SFT(10)
Ladder Symbol
0000
The following timing example uses HR 0 as the results word.
This section describes the instructions that are used to create and manipu-
late shift registers. SFT(10) creates a single- or multiple-word register that
shift in a second execution condition when executed with an ON execution
condition. SFTR(84) creates a reversible shift register that is controlled
through the bits in a control word. WSFT(16) creates a multiple-word register
that shifts by word.
E must be less than or equal to St, and St and E must be in the same data
area.
If a bit address in one of the words used in a shift register is also used in an
instruction that controls individual bit status (e.g., OUT, KEEP(11)), an error
(“COIL DUPL”) will be generated when program syntax is checked on the
Programming Console or another Programming Device. The program, how-
ever, will be executed as written. See Example 2: Controlling Bits in Shift
Registers for a programming example that does this.
0001 0002 0003 0004 0005 0004 0003 0002 0001 0000 9999 9998 9997 0000
I
P
R
SFT(10)
St
E
Operand Data Areas
St : Starting word
E : End word
IR, HR
IR, HR
Section 5-12
0000
0000