C500MP102EV3 Omron, C500MP102EV3 Datasheet - Page 52

• Manufacturer Part Number: C500MP102EV3
• Description: K-TYPE PC MEMORY RACK
• Manufacturer: Omron

Specifications of C500MP102EV3

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Ladder Diagram
40
TR Bits
0000
0000
TR 0
TR 0
Diagram B: Corrected Using a TR bit
0005
0004
0001
0001
0002
There are two means of programming branching programs to preserve the
execution conditions. One is to use TR bits; the other, to use interlocks
(IL(02)/ILC(03)).
The TR area provides eight bits, TR 0 through TR 7, that can be used to tem-
porarily preserve execution conditions. If a TR bit is used as the operand of
the OUTPUT instruction placed at a branching point, the current execution
condition will be stored at the designated TR bit. Storing execution conditions
is a special application of the OUTPUT instruction. When returning to the
branching point, the same TR bit is then used as the operand of the LOAD
instruction to restore the execution condition that existed when the branching
point was first reached in program execution.
The above diagram B can be written as shown below to ensure correct exe-
cution.
In terms of actual instructions the above diagram would be as follows: The
status of 0000 is loaded (a LOAD instruction) to establish the initial execution
condition. This execution condition is then output using an OUTPUT instruc-
tion to TR 0 to store the execution condition at the branching point. The exe-
cution condition is then ANDed with the status of 0001 and instruction 1 is
executed accordingly. The execution condition that was stored at the branch-
ing point is then loaded back in (a LOAD instruction with TR 0 as the oper-
and) and instruction 2 is executed accordingly.
The following example shows an application using two TR bits.
In this example, TR 0 and TR 1 are used to store the execution conditions at
the branching points. After executing instruction 1, the execution condition
stored in TR 1 is loaded for an AND with the status 0003. The execution con-
dition stored in TR 0 is loaded twice, the first time for an AND with the status
of 0004 and the second time for an AND with the inverse of the status of
0005.
TR 1
0002
0003
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 1
Instruction 2
Address Instruction
Address Instruction
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0000
0001
0002
0003
0004
0005
0006
LD
OUT
AND
OUT
AND
OUT
LD
AND
OUT
LD
AND
OUT
LD
AND NOT
OUT
LD
OUT
AND
Instruction 1
LD
AND
Instruction 2
TR
TR
TR
TR
TR
TR
TR
Operands
Operands
Section 4-3
0000
0001
0002
0500
0003
0501
0004
0502
0005
0503
0000
0001
0002
0
1
1
0
0
0
0