C500MP102EV3 Omron, C500MP102EV3 Datasheet - Page 82

• Manufacturer Part Number: C500MP102EV3
• Description: K-TYPE PC MEMORY RACK
• Manufacturer: Omron

Specifications of C500MP102EV3

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Data Areas, Definer Values, and Flags
Multiple Instruction Lines
TR Bits
0200
0201
0000
0000
HR 015
0002
0202
TR
0
0004
0005
1501
0001
0001
0203
TR
1
0003
0002
1500
If a right-hand instruction requires multiple instruction lines, all of the lines for
the instruction are coded before the right-hand instruction. Each of the lines
for the instruction are coded starting with LD or LD NOT to form ‘logic blocks’
that are combined by the right-hand instruction. An example of this for
CNTR(12) is shown below.
TR bits in a program are used to output (OUT) the execution condition at the
branching point and then to load back (LD) the execution condition when it is
required after returning to the branch lines. Within any one instruction block,
OUT cannot be used with the same TR address. The same TR address can,
however, be used with LD as many times as required. The following example
shows an instruction block using two TR bits. TR 1 is used in LD once; TR 0,
twice.
I
P
R
0100
0100
0101
0102
0103
CNTR(12)
#5000
02
Address Instruction
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
Address
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
LD
OUT
AND
OUT
AND
OUT
LD
AND
OUT
LD
AND
OUT
LD
AND NOT
OUT
Instruction
LD
AND
LD
LD
AND NOT
LD
AND NOT
AND NOT
OR LD
AND
CNTR(12)
LD
OUT NOT
TR
TR
TR
TR
TR
Operands
#
HR
Section 5-4
Operands
0000
0001
0002
0100
0003
0101
0004
0102
0005
0103
0
1
1
0
0
0000
0001
0002
0200
0203
0201
0202
1501
1500
5000
0100
015
02
71