XC4010E-3PQ160I Xilinx Inc, XC4010E-3PQ160I Datasheet - Page 39

• Manufacturer Part Number: XC4010E-3PQ160I
• Description: IC FPGA I-TEMP 5V 3SPD 160-PQFP - XC4010E-3PQ160I
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4010E-3PQ160I

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 129
• Number Of Gates: 10000
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 160-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 41 on page 44
boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
XC4000 Series devices can also be configured through the
boundary scan logic. See
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-State Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000X Boundary Scan Logic is Identical.
May 14, 1999 (Version 1.6)
Boundary
Scan
R
Ouput Clock OK
Input Clock IK
Ouput Data O
Clock Enable
I - capture
I - update
3-State TS
OUTPUT
is a diagram of the XC4000 Series
INPUT
Product Obsolete or Under Obsolescence
“Readback” on page
M
M
DELAY
OUTPUT
INVERT
M
M
XC4000E and XC4000X Series Field Programmable Gate Arrays
GLOBAL
S/R
TS/OE
Boundary
Scan
M
M
Boundary
INVERT
S/R
Scan
M
M
TS INV
TS - capture
55.
TS - update
INVERT
S/R
O - capture
Q - capture
O - update
D
EC
M
sd
rd
Q
D
EC
sd
rd
Q
Q
L
FLIP-FLOP/LATCH
OUT
SEL
M
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to imple-
ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
EXTEST
M M
M M
corresponding
SLEW
RATE
Input Data 1 I1
Input Data 2 I2
DOWN
PULL
pins
PULL
UP
V
CC
(BSCAN.TDO1
PAD
X5792
6-43
and
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