AFCT-57J5APZ Avago Technologies US Inc., AFCT-57J5APZ Datasheet - Page 3

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AFCT-57J5APZ

Manufacturer Part Number
AFCT-57J5APZ
Description
SM BTS FP SFP Ind-Temp, RoHS
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of AFCT-57J5APZ

Data Rate
3.072Gbps
Wavelength
1310nm
Applications
General Purpose
Voltage - Supply
2.97 V ~ 3.63 V
Connector Type
LC Duplex
Mounting Type
SFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Transmitter Section
The transmitter section includes consists of the Transmit-
ter Optical SubAssembly (TOSA) and laser driver circuitry.
The TOSA, containing a 1310nm FABRY PEROT light
source, is located at the optical interface and mates with
the LC optical connector. The TOSA is driven by a custom
IC which uses the incoming differential high speed logic
signal to modulate the laser diode driver current. This
Tx laser driver circuit regulates the optical power at a
constant level provided the incoming data pattern is dc
balanced (8B/10B code, for example).
Transmit Disable (Tx_Disable)
The AFCT-57J5APZ accepts a TTL and CMOS compatible
transmit disable control signal input (pin 3) which shuts
down the transmitter optical output. A high signal im-
plements this function while a low signal allows normal
transceiver operation. In the event of a fault (e.g. eye
safety circuit activated), cycling this control signal resets
the module as depicted in Figure 4. An internal pull up
resistor disables the transceiver transmitter until the host
pulls the input low. Host systems should allow a 10ms
interval between successive assertions of this control
signal. Tx_Disable can also be asserted via the two-wire
serial interface (address A2h, byte 110, bit 6) and
monitored (address A2h, byte 110, bit 7).
The contents of A2h, byte 110, bit 6 are logic OR’d with
hardware Tx_Disable (pin 3) to control transmitter
operation..
Transmit Fault (Tx_Fault)
A catastrophic laser fault will activate the transmitter
signal, TX_FAULT, and disable the laser. This signal is
an open collector output (pull-up required on the host
board). A low signal indicates normal laser operation
and a high signal indicates a fault. The TX_FAULT will
be latched high when a laser fault occurs and is cleared
by toggling the TX_DISABLE input or power cycling the
transceiver. The transmitter fault condition can also be
monitored via the two-wire serial interface (address A2,
byte 110, bit 2).
Eye Safety Circuit
The AFCT-57J5APZ provides Class 1 (single fault tolerant)
eye safety by design and has been tested for compliance
with the requirements listed in Table 1. The eye safety
circuit continuously monitors the optical output power
level and will disable the transmitter upon detecting an
unsafe condition beyond the scope of Class 1 certifica-
tion. Such unsafe conditions can be due to inputs from
the host board (Vcc fluctuation, unbalanced code) or a
fault within the transceiver.
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Receiver Section
The receiver section includes the Receiver Optical
SubAssembly (ROSA) and the amplification/quanti-
zation circuitry. The ROSA, containing a PIN photodi-
ode and custom transimpedance amplifier, is located
at the optical interface and mates with the LC optical
connector. The ROSA output is fed to a custom IC that
provides post-amplification and quantization.
Receiver Loss of Signal (Rx_LOS)
The post-amplification IC also includes transition
detection circuitry which monitors the ac level of
incoming optical signals and provides a TTL/CMOS com-
patible status signal to the host (pin 8). An adequate
optical input results in a low Rx_LOS output while a high
Rx_LOS output indicates an unusable optical input. The
Rx_LOS thresholds are factory set so that a high output
indicates a definite optical fault has occurred. Rx_LOS
can also be monitored via the two-wire serial interface
(address A2h, byte 110, bit 1).
Functional Data I/O
The AFCT-57J5APZ interfaces with the host circuit board
through twenty I/O pins (SFP electrical connector) iden-
tified by function in Table 2. The board layout for this
interface is depicted in Figure 6.
The AFCT-57J5APZ high speed transmit and receive in-
terfaces require SFP MSA, OBSAI or CPRI compliant signal
lines on the host board. To simplify board requirements,
biasing resistors and ac coupling capacitors are incorpo-
rated into the SFP transceiver module (per INF-8074) and
hence are not required on the host board. The Tx_Disable,
Tx_Fault, Rx_LOS and Rate_Select lines require TTL lines
on the host board (per INF-8074) if used. If an application
chooses not to take advantage of the functionality of
these pins care must be taken to ground Tx_Disable (for
normal operation) and Rate_Select is set to default in the
proper state.
Figure 2 depicts the recommended interface circuit to
link the AFCT-57J5APZ to supporting physical layer ICs.
Timing for MSA compliant control signals implemented
in the transceiver are listed in Figure 4.

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