AD9957/PCBZ Analog Devices Inc, AD9957/PCBZ Datasheet - Page 33

• Manufacturer Part Number: AD9957/PCBZ
• Description: D/A Converter Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9957/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Direct Digital Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9957
• Kit Contents: Board
• Main Purpose: Timing: DDS Modulators
• Embedded: No
• Utilized Ic / Part: AD9957
• Primary Attributes: 14-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RAM Continuous Recirculate Mode
The continuous recirculate mode mimics ramp-up mode,
except that when the state machine reaches the end address of
the active RAM segment register, it does not halt. Instead, the
next timeout of the internal timer causes the state machine to
jump to the start address of the active RAM segment register.
This process continues indefinitely until an I/O update or state
change on the RT pin. A state change on the RT pin aborts the
current waveform and the newly selected RAM segment register
initiates a new waveform.
A graphic representation of the continuous recirculate mode is
shown in Figure 46.
The circled numbers in Figure 46 indicate specific events, which
are explained as follows:
Event 1—an I/O update or state change on the RT pin occurs.
This initializes the state machine to the start address of the
I/O_UPDATE OR
RT TRANSITION
RAM ADRESS
M DDS CLOCK CYCLES
1 PDCLK CYCLE
1
OR
START ADDRESS
END ADDRESS
Figure 46. Continuous Recirculate Timing Diagram
1
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Δ
t
2
3
active RAM segment register and causes the state machine to
begin incrementing the address counter at the appropriate rate.
Event 2—the state machine reaches the end address of the active
RAM segment register.
Event 3—the state machine switches to the start address of the
active RAM segment register. The state machine continues to
increment the address counter.
Event 4—the state machine again reaches the end address of the
active RAM segment register.
Event 5—the state machine switches to the start address of the
active RAM segment register. The state machine continues to
increment the address counter.
Event 4 and Event 5 repeat until an I/O update or state change
occurs on the RT pin.
4
5
AD9957