AD9957/PCBZ Analog Devices Inc, AD9957/PCBZ Datasheet - Page 4

• Manufacturer Part Number: AD9957/PCBZ
• Description: D/A Converter Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9957/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Direct Digital Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9957
• Kit Contents: Board
• Main Purpose: Timing: DDS Modulators
• Embedded: No
• Utilized Ic / Part: AD9957
• Primary Attributes: 14-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9957
REVISION HISTORY
10/10—Rev. A to Rev. B
Changes to Data Rate in Features Section ..................................... 1
Changes to Specifications Section .................................................. 6
Added EPAD Notation to Figure 4 and Table 3............................ 9
Changes to XTAL_SEL Pin Description ...................................... 11
Changes to BlackFin Interface (BFI) Mode Section .................. 18
Changes to Figure 30 and Figure 31 ............................................. 22
Changes to Programmable Interpolating Filter Section ............ 24
Changes to Fifth Paragraph of Quadrature Modulator Section ..... 25
Changes to RAM Segment Registers Section ............................. 27
Changes to RAM Playback Operation Section ........................... 28
Changes to Control Interface—Serial I/O Section ..................... 47
Added to I/O_UPDATE, SYNC_CLK, and System Clock
Relationships Section and Figure 64 ............................................ 49
Changes to Default Values of Profile 0 Register—Single Tone
(0x0E) and Profile 0 Register—QDUC (0x0E) in Table 14 ....... 51
Changes to Default Values in Table 15 ......................................... 52
Changes to Default Values in Table 16 ......................................... 53
Changes to Default Values in Table 17 ......................................... 54
Updated Outline Dimensions ....................................................... 61
Rev. B | Page 4 of 64
1/08—Rev. 0 to Rev. A
Changes to REFCLK Multiplier Specification ............................... 3
Changes to I/O_Update/Profile<2:0>/RT Timing
Characteristics and I/Q Input Timing Characteristics ................. 5
Replaced Pin Configuration and Function Descriptions
Section ................................................................................................. 8
Changes to Figure 25 Through Figure 29.................................... 15
Deleted Table 4, Renumbered Sequentially ................................ 20
Changes to DDS Core Section ...................................................... 24
Changes to Figure 47 and Table 6................................................. 33
Replaced Synchronization of Multiple Devices Section ............ 39
Added I/Q Path Latency Section .................................................. 44
Added Power Supply Partitioning Section .................................. 45
Changes to General Serial I/O Operation Section ..................... 46
Changes to Table 13 ....................................................................... 48
Changes to Table 14 ....................................................................... 49
Changes to Table 19 ....................................................................... 54
Changes to Table 20 ....................................................................... 56
Changes to GPIO Configuration Register and
GPIO Data Register Sections ........................................................ 58
5/07—Revision 0: Initial Version