IPR-ASI Altera, IPR-ASI Datasheet - Page 29

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix A: Constraints
Minimize Timing Skew
Minimize Timing Skew
January 2011 Altera Corporation
1
1
Specify Clocks that are Exclusive or Asynchronous
The ASI MegaCore function may show timing violations in slower speed grade
devices. These paths are not required to have fast timing, so you can use the following
constraints to remove these timing paths. The command set_clock_groups can be
used.
The following SDC commands are only applicable for Stratix IV, you must use the
constraint entry dialog boxes to constrain for other device families.
■
set_clock_groups -exclusive -group [get_clocks {tx_clk135}] -group
[get_clocks
{asi_megacore_top_inst|asi_tx_gen.u_tx|u_gxb4_tx.u_gxb|alt4gxb_compone
nt|auto_generated|transmit_pcs0|clkout}]
You should minimize the timing skew among the paths from I/O pins to the four
sampling registers (sample_a[0], sample_b[0], sample_c[0], and sample_d[0]). To
minimize the timing skew, manually place the sampling registers close to each other
and to the serial input pin. Because these four registers are using four different clock
domains, place two of the four registers in one LAB and the other two in another LAB.
Furthermore, place the 2 chosen LABs within the same row whatever the placement
of the serial input. Finally, do not place the four sampling registers at the immediate
rows or columns next to the I/O, but the second one next to the I/O bank. This
location is because inter-LAB interconnects between I/O banks and their immediate
rows or columns are much faster than core interconnect.
Optimizing beneficial skew may add unwanted delay to the sampling clocks and
cause performance degradation or failure. To avoid this unwanted delay for all
sampling registers, in the Fitter settings, select Off for Enable Beneficial Skew
Optimization.
The following code is an example of a constraint, which you can set using the
Quartus II Assignment Editor:
set_location_assignment PIN_99 -to asi_rx0
set_location_assignment LC_X32_Y17_N0 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_a[0]"
set_location_assignment LC_X33_Y17_N0 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_b[0]"
set_location_assignment LC_X32_Y17_N1 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_c[0]"
set_location_assignment LC_X33_Y17_N1 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_d[0]"
ASI TX (Hard Transceiver)
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
A–3