IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 7

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Decoder
Altera Corporation
Figure 4. Encoder Timing Diagram
Data and identified 10-bit special K codes are converted from 10 bits to 8
bits; see
page 2
When special 10-bit K codes are received, the special K codes are
translated to 8-bit values, and the kout signal is asserted. The decoder
also checks for invalid 10-bit codes, and asserts the kerr signal when
invalid codes are detected.
When the idle_del signal is asserted, it deletes all 10-bit words
identified as the special IDLE character of K28.5.
When the receiver detects a disparity error, the rderr signal is asserted.
Figure 5
Figure 5. ED8B10B Decoder
clk
datain,
kin,
enable
dataout
rdforce,
rdin
for an illustration of the conversion process.
Table 1 on page 3
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
shows a block diagram of the decoder.
datain [9:0]
idle_del
reset_n
rdforce
a
enable
rdin
clk
n
b
for a list of the valid K codes, and
n+1
c
a
n+2
d
a
b
n+3
valid
dataout [7:0]
kout
kerr
rderr
rdout
rdcascade
e
b
c
Figure 1 on
d
c
f
g
d
e
7