IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 9

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

I/O Signals
Altera Corporation
clk
reset_n
kin
enable
idle_ins
datain[7:0]
rdin
rdforce
kerr
dataout[9:0]
valid
rdout
rdcascade
clk
reset_n
idle_del
enable
datain[9:0]
Table 2. Encoder I/O Signals
Table 3. Decoder I/O Signals
Signal Name
Signal Name
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Direction
Direction
Tables 2
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
and
Clock. The input is latched, and the result is output on this clock. There
is a three clock cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the core.
Command byte indicator. When high, indicates that the input is a
command byte, not a data byte.
Enable encoder signal. When high, indicates that the data currently
present on the datain input is to be encoded.
Idle character insert. When high, idle (K28.5) characters are inserted
when enable is not asserted.
Data input. This is the 8-bit input word, data or command.
Running disparity input. When rdforce is high, the value on this pin is
used as the current running disparity instead of the internally generated
one.
Force running disparity. When high, the rdin value overrides the
internally generated running disparity.
Special K character error. This signal is set high when enable and kin
are high and the value on datain is not a valid special K character.
Data output. This is the 10-bit encoded output.
Valid signal. When high, indicates that a valid encoded word is present
on the dataout output.
Running disparity output. The current running disparity (after encoding
the word present on the dataout output).
Cascaded Running disparity. Used when encoders are cascaded.
Clock. The input is latched, and the result output on this clock. There is
a three clock cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the core.
Idle delete signal. When high, idle words (K28.5) are removed from the
stream (i.e. valid is set low when idle words are received).
Enable decoder signal. When high, indicates that the data currently
present on the datain input is to be decoded.
Data input. This is the 10-bit encoded input word.
3
list the input/output signals for the encoder, and decoder.
Description
Description
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