IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 168
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 168 of 362
- Download datasheet (7Mb)
7–8
Figure 7–6. Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix IV GX, Stratix V GX ×1, ×4, or ×8 100 MHz Reference
Clock
Note to
(1) Different device families require different frequency ranges for the calibration and reconfiguration clocks. To determine the frequency range for
PCI Express Compiler User Guide
your device, refer to one of the following device handbooks:
in Volume 2 of the Cyclone IV Device Handbook,
Guide
Figure
for Stratix V devices.
7–6:
Clock Source
Clock Source
Clock Source
Clock Source
Calibration
100-MHz
Reconfig
Fixed
Figure 7–6
The IP core contains a clock domain crossing (CDC) synchronizer at the interface
between the PHY/MAC and the DLL layers which allows the data link and
transaction layers to run at frequencies independent of the PHY/MAC and provides
more flexibility for the user clock interface to the IP core. Depending on system
requirements, this additional flexibility can be used to enhance performance by
running at a higher frequency for latency optimization or at a lower frequency to save
power.
illustrates this clocking configuration.
<variant>.v or .vhd
refclk
Transceiver Architecture
<variant>_serdes.v or .vhd
rx_cruclk
pll_inclk
cal_blk_clk
reconfig_clk
fixedclk
(PCIe MegaCore Function)
<variant>_core.v or .vhd
(ALTGX or ALT2GX
Transceiver Architecture
Megafunction)
tx_clk_out
in Volume 2 of the Stratix IV Device Handbook, or
in Volume II of the Arria II Device Handbook,
125 MHz - x1 or x4
core_clk_out
250 MHz - x8
December 2010 Altera Corporation
Chapter 7: Reset and Clocks
Application Clock
Altera PHY IP User
Transceivers
Clocks
Related parts for IPR-PCIE/4
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE RENEW
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-XAUIPCS
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: