CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 26

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

26
5. APPLICATIONS
5.1
Power Down ADC
Power Down DAC
Power Down Device
MCLK Frequency Select
Freeze Control
AUX Serial Port Interface Format
ADC1/ADC2 High Pass Filter Freeze
ADC3 High Pass Filter Freeze
DAC De-Emphasis
ADC1/ADC2 Single-Ended Mode
ADC3 Single-Ended Mode
AIN5 Multiplexer
Overview
The CS42438 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital con-
verters (ADC) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (DAC)
also implemented using multi-bit delta-sigma techniques.
Other functions integrated within the CODEC include independent digital volume controls for each DAC, dig-
ital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-pass
filters, and an on-chip voltage reference,.
The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Multi-
plexed (TDM) interface format. The CS42438 features an Auxiliary Port used to accommodate an additional
two channels of PCM data on the ADC_SDOUT data line in the TDM digital interface format. See
Digital Interface Formats” on page 34
The CS42438 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined automatically based on the MCLK frequency setting. Single-Speed Mode (SSM) supports in-
put sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports
input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) sup-
ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x (Note: QSM for the ADC is
only supported in the I²S, Left-Justified, Right-Justified interface formats. QSM is not supported for the
ADC). Note: QSM is only available in Software Mode (see
All functions can be configured through software via a serial control port operable in SPI Mode or in I²C
Mode. A Hardware, Stand-Alone Mode is also available, allowing configuration of the CODEC on a more
limited basis. See Table 2 for the default configuration in Hardware Mode.
Figure 1 on page 11
Software and Hardware Mode, respectively. See
settings and options in Software Mode.
Function
and
Figure 2 on page 12
Table 2. Hardware Configurable Settings
Hardware Mode Feature Summary
Selectable between 256Fs and
Selectable between Differential
AIN5B when ADC3 in Single-
Selects between AIN5A and
High Pass Filter is always
Default Configuration
No De-Emphasis applied
High Pass Filter can be
All ADC’s are enabled
All DAC’s are enabled
Device is powered up
for details.
and Single-Ended
enabled/disabled
Left-Justified
Ended Mode
Disabled
enabled
512Fs
N/A
show the recommended connections for the CS42438 in
“Register Description” on page 41
“System Clocking” on page 33
ADC3_SINGLE” pin 13
Hardware Control
“ADC3_HPF” pin 4
“AIN5_MUX” pin 1
“ADC_SDOUT/
“MFREQ” pin 3
-
-
-
-
-
-
-
-
for the default register
-
-
-
see
-
-
-
see
-
-
see
see
for details).
Section 5.4
Section 5.2.5
Section 5.2.2
Section 5.2.2
CS42438
Note
“AUX Port
DS646F2