CDB42438 Cirrus Logic Inc, CDB42438 Datasheet
CDB42438
Specifications of CDB42438
Related parts for CDB42438
CDB42438 Summary of contents
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... S/PDIF Input Osc. Cirrus Logic, Inc. www.cirrus.com Description The CDB42438 evaluation board is an excellent means for evaluating the CS42438 CODEC. Evaluation re- quires an analog/digital signal source and analyzer, and power supplies. Optionally, a Windows computer may be used to evaluate the CS42438 in soft- ware mode. ...
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... TDMer MCLK ...................................................................................................... 13 3.6 Bypass Control - Advanced ............................................................................................. 14 4. FPGA REGISTER QUICK REFERENCE ............................................................................... 15 5. FPGA REGISTER DESCRIPTION ......................................................................................... 16 6. HARDWARE MODE ............................................................................................................... 24 6.1 Setup Options .................................................................................................................. 24 7. CDB CONNECTORS AND JUMPERS ................................................................................... 27 8. CDB BLOCK DIAGRAM 9. CDB SCHEMATICS 10. CDB LAYOUT ................................................................................................................... 48 11. REVISION HISTORY ............................................................................................................ 51 2 ................................................................................................... 29 ............................................................................................................. 30 CDB42438 DS646DB2 ...
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... Figure 24. Analog Output 7-8........................................................................................................ 46 Figure 25. Power........................................................................................................................... 47 Figure 26. Silk Screen................................................................................................................... 48 Figure 27. Top side Layer ............................................................................................................. 49 Figure 28. Bottom side Layer ........................................................................................................ 50 LIST OF TABLES Table 1. Data to SDIN ................................................................................................................... 16 Table 2. Clocks toCODEC ............................................................................................................ 17 Table 3. Data to CS8406............................................................................................................... 17 Table 4. Data to DSP .................................................................................................................... 20 Table 5. System Connections ....................................................................................................... 27 Table 6. Jumper Settings .............................................................................................................. 28 Table 7. Revision History .............................................................................................................. 51 DS646DB2 CDB42438 3 ...
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... The CDB42438 evaluation board is an excellent means for evaluating the CS42438 CODEC. An- alog and digital audio signal interfaces are provided, an FPGA used for easily configuring the board and a 9-pin serial cable for use with the supplied Windows The CDB42438 schematic set has been partitioned into 18 pages and is shown in Figures 8 through 25. 1.1 Power Power must be supplied to the evaluation board through the +5 ...
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... External Control Headers The evaluation board has been designed to allow interfacing with external systems via the headers J11 and J24. The 10-pin, 2 row header, J24, provides access to the serial audio signals required to inter- face with a DSP (see Figure 9 on page 31). DS646DB2 CDB42438 5 ...
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... Serial Control Port A graphical user interface is included with the CDB42438 to allow easy manipulation of the registers in the CS42438 (see the CS42438 data sheet for register descriptions) and FPGA (see section 5 on page 16 for register descriptions). Connecting a cable to the RS-232 con- nector (J7) and launching the Cirrus Logic FlexGUI software will enable the CDB42438. Refer to “ ...
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... Once the appropriate cable is connected between the CDB42438 and the host PC, load “Flex- Loader.exe” from the CDB42438 directory. Once loaded, all registers are set to their default re- set state. The GUI’s “File” menu provides the ability to save and load script files containing all of the register settings ...
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... Figure 2. Advanced Register Tab - FPGA CDB42438 DS646DB2 ...
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... S/PDIF In, S/PDIF Out (SPDIF1-4) This script sets up the CDB42438 to operate the CS8416 as the master and all other de- vices as slave. The CS8416 masters the MCLK bus. Various permutations of this option exist as S/PDIF1, S/PDIF2, S/PDIF3 and S/PDIF4. Each permutation signifies which ADC data is transmitted to the CS8406. ...
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... AUX LRCK CS8416 SCLK SCLK AUX SCLK DSP Header DSP_FS DSP FS DSP_SCLK DSP SCLK CS8406 LRCK TDMer SCLK 10 DSP_FS FS DSP_SCLK 256Fs FS 256Fs Figure 3. Internal Sub-Clock Routing CDB42438 CS42438 CODEC_CLK.MUX[1:0] FPGA->CODEC FS CODEC_CLK.MUX[1:0] FPGA->CODEC SCLK AUX LRCK AUX_LRCK AUX SCLK AUX_SCLK DS646DB2 ...
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... DSP Header DSP_DOUT DSP_DIN DATA_MUX[2:0] CS8406 ADC1 ADC2 ADC3 SDIN AUX MUX[2:0] CS8416 SDOUT DS646DB2 DSP OUT SDOUT TDM Stream ADC1,2,3, AUX TDMer TDM Stream Figure 4. Internal Data Routing CDB42438 CS42438 SDIN_MUX[1:0] DSPDATA->DAC SDIN SDOUT AUX_SDIN 11 ...
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... CS42438 is de-multiplexed and transmitted to the CS8406. The TDMer is also capable of transmitting the de-multiplexed data to the DSP Header; however, the user must re-time this data using a DSP. The CDB42438 does not provide an option for rout- ing the TDM2PCM clocks to the DSP Header. ...
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... External MCLK Control Several sources for MCLK exist on the CDB42438. The crystal oscillator, Y1, will master the MCLK bus when no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for details on OMCK operation). This signal will be driven directly out the CS8416. ...
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... DATA->DAC” and “SDOUT->DSP” should also be set to ‘0’b in bypass mode. NOTE: To avoid contention with the FPGA, set the clock direction for the FPGA appropriately: The FPGA->CO- DEC bits in register 03h must be set to ‘1’b. 14 CDB42438 DS646DB2 ...
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... Reserved Reserved Reserved MUX2 MUX1 Reserved RST Reserved CS5341 ->AUX DATA_MUX2 DATA_MUX1 DATA_MUX0 INT.MCLK_ OMCK/DIV_ ‘41_MCLK_ DIV 1.5 CDB42438 Reserved Reserved Reserved Reserved Reserved SDIN.MUX1 Reserved CLK_MUX1 CLK_MUX0 FPGA->CODEC MUX0 128/256 Fs I²S/ M/S 128/256 Fs I²S/ Reserved Reserved Reserved ...
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... This MUX selects the data lines from the DSP Header, the ADC and the TDM Stream from the TDMer (see Figure 4 on page 11 Reserved Reserved Reserved Reserved SDIN.MUX[1:0] Data Selection 00 Reserved 01 DSP_DOUT 10 ADC_SDOUT 11 TDM Stream Table 1. Data to SDIN CDB42438 Reserved Reserved PDN_TDMer Reserved SDIN.MUX1 SDIN.MUX0 DS646DB2 ...
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... MUX1 MUX0 MUX[2:0] Data Selection 000 Reserved 001 Reserved 010 Reserved 011 Reserved 100 ADC1 (from ADC_SDOUT) 101 ADC2 (from ADC_SDOUT) 110 ADC3 (from ADC_SDOUT) 111 EXT_ADC (from ADC_SDOUT) Table 3. Data to CS8406 CDB42438 CLK_MUX1 CLK_MUX0 FPGA->CODEC 128/256 Fs I²S/LJ Reserved 17 ...
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... MASTER/SLAVE SELECT (M/S) Default = Slave 1 - Master Function: Selects master/slave mode for the CS8416 and configures the internal routing buffers. Pin 6 (RST bit) 18 ² S INTERFACE FORMAT ( RST M/S CDB42438 ² S/LJ 128/256 Fs I²S/LJ RMCK_Master 0 DS646DB2 ...
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... BYPASS FPGA (BYPASSFPGA) Default = Enable 1 - Disable Function: This bit toggles a control line for the external data buffer to route the DSP directly to the CODEC. DS646DB2 ² S INTERFACE FORMAT ( CS5341 Reserved ->AUX CDB42438 ² S/LJ Reserved Reserved 0 Reserved 19 ...
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... DSP SDIN 000 ADC_SDOUT 001 ADC1 (from ADC_SDOUT) 010 ADC2 (from ADC_SDOUT) 011 ADC3 (from ADC_SDOUT) 100 EXT_ADC (from ADC_SDOUT) 101 ADC1 (from ADC_SDOUT) 110 ADC2 (from ADC_SDOUT) 111 ADC3 (from ADC_SDOUT) Table 4. Data to DSP CDB42438 2 1 Reserved Reserved MCLK_M/S DS646DB2 0 ...
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... DSP MCLK (MCLK_M/S) Default = DSP MCLK is a slave to the MCLK bus DSP MCLK masters MCLK bus. Function: Enables/disables the external DSP MCLK output buffer on the MCLK bus. DS646DB2 CDB42438 21 ...
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... Divide by 2.0 Function: Divides the MCLK from the MCLK bus to the CS5341 by 1 (see Figure 6 on page 13). 5.8.5 LEFT-JUSTIFIED OR I Default = Left Justified ² INT.DIV_ ‘41_MCLK_ DIV 1.5/2 DIV ² S INTERFACE FORMAT (‘41_I CDB42438 ‘41_DIV_ ‘41_I²S/LJ ‘41_RST 1.5/2 ² S/LJ) DS646DB2 ...
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... RESET (‘41_RST) Default = CS5341 is held in reset 1 - CS5341 is taken out of reset Function: This bit toggles pin 30 of the FPGA and is held low for 300 µs upon FPGA initialization. It will also be held low for 300 µs whenever register 08h[1] changes. DS646DB2 CDB42438 23 ...
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... HARDWARE MODE Switch S1 configures the CDB42438 in hardware mode. Switch S5 sets up the FPGA and con- trols the routing of all clocks and data. Refer to section 6.1 for a list of the various hardware mode options available. After setting any of these switches, the user may need to assert a reset by pressing the “ ...
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... CODEC Clock Control - N/A. 04h 01h CS8406 Control - N/A. 05h 29h CS8416 Control - N/A. 06h 0Ch Bypass Control - DSP to CODEC. 07h 07h Misc. Control - DSP Master. 08h 41h CS5341 Control - Left-justified data from CS5341. Maximum MCLK = 25 MHz. Reserved Reserved Reserved CDB42438 25 ...
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... CS8416 to MCLK bus and CS8416 provides PCM subclocks to the TDMer. [S/PDIF input must be removed] 06h EFh Bypass Control - N/A. 07h 08h Misc. Control - DSP Slave to MCLK. 08h 41h CS5341 Control - Left-justified data from CS5341. Maximum MCLK = 25 MHz. CDB42438 DS646DB2 ...
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... RCA phono jacks for analog input signal to CS42438. Input RCA phono jacks for analog input signal to CS5341. Input RCA phono jacks for analog outputs. Output Table 5. System Connections CDB42438 SIGNAL PRESENT 2 C control port signals 2 C control port signals control port signals. ...
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... Inverted signal from AIN2 input SINGLE IN VA/2 voltage bias *DIFF IN Inverted signal from AIN3 input SINGLE IN VA/2 voltage bias *DIFF IN Inverted signal from AIN4 input SINGLE IN VA/2 voltage bias *A 2-Pole Active Filter P Single-Pole Passive Filter Table 6. Jumper Settings CDB42438 FUNCTION SELECTED *Default factory settings DS646DB2 ...
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... CDB BLOCK DIAGRAM Clocks/Data DS646DB2 CDB42438 Data & Clocks 29 ...
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... CDB SCHEMATICS 30 CDB42438 DS646DB2 ...
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... CDB LAYOUT 48 CDB42438 DS646DB2 ...
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... R237 from 6.19 kΩ to 4.75 kΩ on Figure 21 on page 43, Figure 22 on page 44, Figure 23 on page 45, Figure 24 on page 46. Layer Changes: Corrected silk screen lables for S1, J8, J11, and J24 on Fig- ure 26 on page 48. Changed bottom layer lot number on Figure 28 on page 50. Table 7. Revision History CDB42438 Changes 51 ...