CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 19

Eval Bd LP Codec W/Class D Spkr Driver

CDB42L52

Manufacturer Part Number
CDB42L52
Description
Eval Bd LP Codec W/Class D Spkr Driver
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB42L52

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42L52
Primary Attributes
4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
Secondary Attributes
GUI, I2C, SPI, USB Interfaces
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS42L52
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1505
DS680F1
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Frequency = 48 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz; Test load R
on page 37
AOUTx Power Into R
HP_GAIN[2:0]
011 (default)
000
001
010
100
101
110
111
11. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
written on power up.
may not achieve the full THD+N performance at full-scale output voltage and power.
Parameters
Gain (G)
Analog
0.3959
0.4571
0.6047
0.7099
0.8399
1.0000
1.1430
0.5111
L
= 16
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
VHP
AGND
Figure 2. Headphone Output Test Load
AOUTx
Min
-
-
-
-
-
-
-
-
0.022 µF
51 Ω
L
(Note
= 16 Ω, C
VA = 2.5V
(Note 11)
(Note 11)
5/13/08
Typ
14
14
19
19
23
23
32
44
7, 11) See
C
L
L
= 10 pF (see
Max
Figures 22
-
-
-
-
-
-
-
-
R
L
Figure
(Note
Min
and
-
-
-
-
-
-
-
-
-
-
-
2);
7),
23 on page 74
“Required Initialization Settings”
VA = 1.8V
Figure 22 on page 74
Typ
10
10
12
12
17
17
23
23
32
7
7
Max
-
-
-
-
-
-
-
-
-
-
-
CS42L52
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Unit
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
19

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