CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 70

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

70
6.35.3 Noise Gate Threshold and Boost
6.35.4 Noise Gate Delay Timing
6.36
6.36.1 Serial Port Clock Error (Read Only)
Reserved
7
Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
THRESH sets the threshold level of the noise gate. Input signals below the threshold level will be attenu-
ated to -96 dB. NG_BOOST configures a +30 dB boost to the threshold settings.
Sets the delay time before the noise gate attacks.
Note:
x Analog Soft Ramp” on page
the respective disable bit
page
Indicates the status of the MCLK to LRCK ratio.
Note:
nizes.
NGDELAY[1:0]
00
01
10
11
Application:
SPCLKERR
0
1
Application:
THRESH[2:0]
000
001
010
011
100
101
110
111
Application:
56) is enabled.
SPCLKERR
The Noise Gate attack rate is a function of the sampling frequency, Fs, and the ANLGSFTx
On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
6
Minimum Setting (NG_BOOST = ‘0’b)
-64 dB
-67 dB
-70 dB
-73 dB
-76 dB
-82 dB
Reserved
Reserved
“Noise Gate” on page 28
Delay Setting
50 ms
100 ms
150 ms
200 ms
“Noise Gate” on page 28
Serial Port Clock Status:
MCLK/LRCK ratio is valid.
MCLK/LRCK ratio is not valid.
“Serial Port Clocking” on page 34
DSPAOVFL
5
(“ALCx Soft Ramp Disable” on page 55
49) and ANLGZCx
DSPBOVFL
4
5/13/08
PCMAOVFL
(“Ch. x Analog Zero Cross” on page
3
Minimum Setting (NG_BOOST = ‘1’b)
-34 dB
-37 dB
-40 dB
-43 dB
-46 dB
-52 dB
-58 dB
-64 dB
PCMBOVFL
2
or
“ALCx Zero Cross Disable” on
ADCAOVFL
1
49) setting unless
CS42L52
ADCBOVFL
DS680F1
0
(“Ch.