CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 8

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

8
3 CONFIGURATION OPTIONS
This section highlights two common configurations for the CDB42L55. It provides a basic understanding of how the
various components on the board work together.
3.1
S/PDIF
IN
S/PDIF or PSIA In to Analog Out
The CS42L55 analog back-end performance can be tested by selecting the “SPDIF In to Analog Out --
Analog In to S/PDIF Out” or “PSIA In to Analog Out -- Analog In to PSIA Out” quick setup file provided
with the software package. Note: The Control Port Compensation script for the associated VA supply
must also be selected. The script configures the digital clock and data signal routing on the board as shown
in
is populated in Y1.
A S/PDIF input must be provided as the S/PDIF Tx (CS8406) uses the RMCK signal from the S/PDIF Rx
(CS8416) for synchronization in this configuration.
PSIA Tx (J78)
Figure
S/PDIF Rx
(CS8416)
(Master)
RX.LRCK
RX.SDOUT
RX.SCLK
TX.LRCK
TX.SDOUT
TX.SCLK
2. The quick setup scripts provided in the software assume that a 24.000 MHz on-board oscillator
Out
Out
FPGA
Figure 2. S/PDIF or PSIA In to Analog Out
(CS8421)
Tx SRC
(Slave)
An on-board PLL generates all supported sample and
bit clock rates from an on-board 24 MHz oscillator.
LRCK
SCLK
DAC.SDIN
CS42L55
(Slave)
MCLK
PLL
LINEOUTB
LINEOUTA
HPOUTB
HPOUTA
J12
J4
32
32
16
16
J21
(on-board osc.)
24 MHz
Connection
HP
CDB42L55
DS773DB1
J3
J2
Channel
Channel
Line
HP
A
B
A
B