CDB5461AU Cirrus Logic Inc, CDB5461AU Datasheet - Page 35

• Manufacturer Part Number: CDB5461AU
• Description: Eval Bd Sngl Phase Power/Energy
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5461AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5461A
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI, Microwire Interfaces
• Processor To Be Evaluated: CS5461A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1552

7. SYSTEM CALIBRATION
7.1 Channel Offset and Gain Calibration
The CS5461A provides digital DC offset and gain com-
pensation that can be applied to the instantaneous volt-
age and current measurements, and AC offset
compensation to the voltage and current RMS calcula-
tions.
Since the voltage and current channels have indepen-
dent offset and gain registers, system offset and/or
gain can be performed on either channel without the
calibration results from one channel affecting the oth-
er.
The computational flow of the calibration sequences are
illustrated in
age channel and current channel.
7.1.1 Calibration Sequence
The CS5461A must be operating in its active state and
ready to accept valid commands. Refer to
Commands
dependent on the value N in the Cycle Count Register
(see
bration are available in their corresponding register. The
DRDY bit in the Status Register will be set. If the DRDY
bit is to be output on the INT pin, then DRDY bit in the
Mask Register must be set. The initial values stored in
the AC gain and offset registers do affect the calibration
results.
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines
the number of conversions performed by the CS5461A
during a given calibration sequence. For DC offset and
gain calibrations, the calibration sequence takes at least
N + 30 conversion cycles to complete. For AC offset
DS661F2
Figure
9). Upon completion, the results of the cali-
In
on page 23. The calibration algorithms are
Figure
Modulator
9. The flow applies to both the volt-
Filter
-1
DC Offset*
+
+
X
+
Figure 9. Calibration Data Flow
Section 5.14
Gain*
X
Inverse
to V*, I* Registers
Σ
÷
N
calibrations, the sequence takes at least 6N + 30 ADC
cycles to complete, (about 6 computation cycles). As N
is increased, the accuracy of calibration results will in-
crease.
7.1.2 Offset Calibration Sequence
For DC- and AC offset calibrations, the VIN± pins of the
voltage and IIN± pins of the current channels should be
connected to their ground-reference level.
See
The AC offset registers must be set to the default
(0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC
offset calibration. Initiate a DC offset calibration. The DC
offset registers are updated with the negative of the av-
erage of the instantaneous samples taken over a com-
putational cycle. Upon completion of the DC offset
calibration the DC offset is stored in the corresponding
DC offset register. The DC offset value will be added to
each instantaneous measurement to cancel out the DC
N
CM + -
X
0V + -
Figure
External
Connections
Figure 10. System Calibration of Offset.
AIN+
AIN-
Σ
10.
N
RMS
0.6
÷
N
* Denotes readable/writable register
√
+
-
-1
XGAIN
AC Offset*
+
+
X
+
V
Registers
RMS
CS5461A
*, I
RMS
*
+
-
35