CDB5461AU Cirrus Logic Inc, CDB5461AU Datasheet - Page 9

• Manufacturer Part Number: CDB5461AU
• Description: Eval Bd Sngl Phase Power/Energy
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5461AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5461A
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI, Microwire Interfaces
• Processor To Be Evaluated: CS5461A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1552

DIGITAL CHARACTERISTICS
•
•
•
•
Notes:
DS661F2
Master Clock Characteristics
Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Filter Characteristics
Phase Compensation Range
Input Sampling Rate
Digital Filter Output Word Rate
High-pass Filter Corner Frequency
Full Scale Calibration Range (
Channel-to-channel Time-shift Error
Input/Output Characteristics
High-level Input Voltage
Low-level Input Voltage (VD = 5 V)
Low-level Input Voltage (VD = 3.3 V)
High-level Output Voltage
Low-level Output Voltage
Input Leakage Current
3-state Leakage Current
Digital Output Pin Capacitance
Min / Max characteristics and specifications are guaranteed over all
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
10.
11. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.
12. The frequency of CPUCLK is equal to MCLK.
13. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
14. Configuration Register bits PC[6:0] are set to “0000000”.
15. The MODE pin is pulled low by an internal resistor.
9. All measurements performed under static conditions.
XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.
full-scale signal applied to the channel input.
If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
All Pins Except XIN and SCLK and RESET
All Pins Except XIN and SCLK and RESET
All Pins Except XIN and SCLK and RESET
Parameter
Internal Gate Oscillator (Note 10) MCLK
Referred to Input
(Voltage Channel, 60 Hz)
SCLK and RESET
SCLK and RESET
SCLK and RESET
DCLK = MCLK/K
(Note 11 and 12)
(Both Channels) OWR
)
I
I
out
out
(Note 13) FSCR
(Note 14)
(Note 15)
= +5 mA
= -5 mA
-3 dB
XIN
XIN
XIN
Symbol
V
C
V
V
I
V
V
I
OZ
Recommended Operating Conditions
OH
OL
in
out
IH
IL
IL
(VD+) - 0.5
(VD+) - 1.0
0.6 VD+
0.8 VD+
Min
-2.8
2.5
40
40
25
-
-
-
-
-
-
-
-
-
-
-
-
-
DCLK/1024
DCLK/8
4.096
Typ
0.5
1.0
±1
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2 VD+
0.2 VD+
CS5461A
.
Max
+2.8
0.48
100
±10
±10
0.8
1.5
0.3
0.4
20
60
60
-
-
-
-
-
-
-
-
%F.S.
MHz
Unit
Hz
Hz
Hz
µA
µA
µs
pF
%
%
V
V
V
V
V
V
V
V
V
V
V
°
9