CDK5581 Cirrus Logic Inc, CDK5581 Datasheet - Page 28

• Manufacturer Part Number: CDK5581
• Description: KIT - CDB558 W/ Capture Plus II System
• Manufacturer: Cirrus Logic Inc
• Series: CapturePLUS™IIr

Specifications of CDK5581

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: ±2.048 V
• Power (typ) @ Conditions: 85mW @ 200kSPS
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5581
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1574

4. PIN DESCRIPTIONS
28
VREF+, VREF- – Voltage Reference Input, Pins 9, 10
SMODE – Serial Mode Select, Pin 3
BUFEN – Buffer Enable, Pin 8
ACOM – Analog Return, Pin 5
TST – Factory Test, Pin 2
V1+ – Positive Power 1, Pin 7
AIN – Analog Input, Pin 4
V1- – Negative Power 1, Pin 6
CS – Chip Select, Pin 1
Voltage Reference Input
Voltage Reference Input
Logic Interface Return 2
Bipolar/Unipolar Select
The Chip Select pin allows an external device to access the serial port. When held high, the
SDO output will be held in a high-impedance output state.
For factory use only. Connect to VLR.
The serial interface mode pin (SMODE) dictates whether the serial port behaves as a master or
slave interface. If SMODE is tied high (to VL), the port will operate in the Synchronous
Self-Clocking (SSC) mode. In SSC mode, the port acts as a master in which the converter out-
puts both the SDO and SCLK signals. If SMODE is tied low (to VLR), the port will operate in the
Synchronous External Clocking (SEC) mode. In SEC mode, the port acts as a slave in which
the external logic or microcontroller generates the SCLK used to output the conversion data
word from the SDO pin.
AIN is the single-ended input.
ACOM is the analog return for the input signal.
The V1- and V2- pins provide a negative supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1- and V2- should
be supplied from the same source voltage. For single-supply operation, these two voltages are
nominally 0 V (Ground). For dual-supply, operation they are nominally -2.5 V.
The V1+ and V2+ pins provide a positive supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should
be supplied from the same source voltage. For single-supply operation, these two voltages are
nominally +5 V. For dual-supply operation, they are nominally +2.5 V.
Buffers on input pins AIN and ACOM are enabled if BUFEN is connected to V1+ and disabled if
connected to V1-.
A differential voltage reference input on these pins functions as the voltage reference for the
converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with
4.096 volts being the nominal reference voltage value.
Serial Mode Select
Negative Power 1
Positive Power 1
Analog Return
Buffer Enable
Analog Input
Factory Test
Chip Select
SMODE
BUFEN
VREF+
ACOM
BP/UP
VREF-
VLR2
TST
V1+
AIN
V1-
CS
1
2
3
4
5
6
7
8
9
10
11
12
3/26/08
10:50
24
23
22
21
20
19
18
17
16
15
14
13
RDY
SCLK
SDO
VL
VLR
MCLK
V2-
V2+
DCR
CONV
VLR3
RST
Ready
Serial Clock Input/Output
Serial Data Output
Logic Interface Power
Logic Interface Return
Master Clock
Negative Voltage 2
Positive Voltage 2
Digital Core Regulator
Convert
Logic Interface Return 3
Reset
CS5581
DS796PP1