CDK5581 Cirrus Logic Inc, CDK5581 Datasheet - Page 6

• Manufacturer Part Number: CDK5581
• Description: KIT - CDB558 W/ Capture Plus II System
• Manufacturer: Cirrus Logic Inc
• Series: CapturePLUS™IIr

Specifications of CDK5581

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: ±2.048 V
• Power (typ) @ Conditions: 85mW @ 200kSPS
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5581
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1574

SWITCHING CHARACTERISTICS
T
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
6
Master Clock Frequency
Master Clock Duty Cycle
Reset
RST Low Time
RST rising to RDY falling
Conversion
CONV Pulse Width
BP/UP setup to CONV falling
CONV low to start of conversion
Perform Single Conversion (CONV high before RDY falling)
Conversion Time
A
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
10. If CONV is held low continuously, conversions occur every 80 MCLK cycles.
8. Reset must not be released until the power supplies and the voltage reference are within specification.
9. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
If RDY is tied to CONV, conversions will occur every 82 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 84 MCLKs.
RDY falls at the end of conversion.
Parameter
Start of Conversion to RDY falling
Internal Oscillator
Internal Oscillator
External Clock
External Clock
3/25/08
14:34
(Note 10)
(Note 8)
(Note 9)
Symbol
t
t
XIN
t
t
t
t
t
f
wup
cpw
bus
buh
scn
scn
res
clk
Min
0.5
12
40
20
1
4
0
-
-
-
-
1536
Typ
120
14
16
-
-
-
-
-
-
-
Max
16.2
16
60
84
2
-
-
-
-
-
-
CS5581
DS796PP1
MCLKs
MCLKs
MCLKs
MCLKs
MCLKs
MHz
MHz
Unit
µs
µs
ns
%