CDK5581 Cirrus Logic Inc, CDK5581 Datasheet - Page 8

KIT - CDB558 W/ Capture Plus II System

CDK5581

Manufacturer Part Number
CDK5581
Description
KIT - CDB558 W/ Capture Plus II System
Manufacturer
Cirrus Logic Inc
Series
CapturePLUS™IIr
Datasheets

Specifications of CDK5581

Number Of Adc's
1
Number Of Bits
16
Sampling Rate (per Second)
200k
Data Interface
Serial
Inputs Per Adc
2 Single
Input Range
±2.048 V
Power (typ) @ Conditions
85mW @ 200kSPS
Voltage Supply Source
Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS5581
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1574
SWITCHING CHARACTERISTICS
T
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
8
Serial Port Timing in SSC Mode (SMODE = VL)
Data hold time after SCLK rising
Serial Clock (Out)
(Note 13, 14)
RDY rising after last SCLK rising
CS falling to MSB stable
First SCLK rising after CS falling
CS hold time (low) after SCLK rising
SCLK, SDO tristate after CS rising
SCLK(o)
A
MCLK
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
SDO
RDY
CS
13. SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down
14. SCLK = MCLK/2.
resistors.
Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)
t
11
Parameter
t
12
MSB
MSB–1
Pulse Width (high)
Pulse Width (low)
t
(CONTINUED)
7
3/25/08
14:34
t
Symbol
8
t
t
t
t
t
t
t
t
10
12
13
14
11
7
8
9
t
9
Min
50
50
10
-
-
-
-
-
LSB+1
t
13
LSB
Typ
10
10
8
8
5
-
-
-
t
14
t
10
Max
-
-
-
-
-
-
-
-
CS5581
DS796PP1
MCLKs
MCLKs
Unit
ns
ns
ns
ns
ns
ns

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