PCF8577CTD NXP Semiconductors, PCF8577CTD Datasheet - Page 10

• Manufacturer Part Number: PCF8577CTD
• Description: LCD Drivers 64 SGMT LCD SGMT DRV
• Manufacturer: NXP Semiconductors

Specifications of PCF8577CTD

• Number Of Segments: 32
• Maximum Clock Frequency: 100 KHz
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Power Dissipation: 500 mW
• Package / Case: VSO-40
• Maximum Supply Current: 125 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PCF8577CT/3,112

Philips Semiconductors
7
The I
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the I
7.1
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
7.2
Both data and clock lines remain HIGH when the I
is not busy. A HIGH-to-LOW transition of the data line,
while the clock is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the stop condition (P).
7.3
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
1998 Jul 30
LCD direct/duplex driver with
I
2
CHARACTERISTICS OF THE I
C-bus interface
2
C-bus is for 2-way, 2-line communication between
Bit transfer
Start and stop conditions
System configuration
SDA
SCL
2
C-bus is not busy.
2
C-BUS
data valid
data line
stable;
2
Fig.8 Bit transfer.
C-bus
10
allowed
change
of data
7.4
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the I
the transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, set-up and hold times must be
taken into account. A master receiver must signal an end
of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a stop
condition.
Acknowledge
MBA607
Product specification
PCF8577C
2
C-bus by