LFE2-50E-VID-EV Lattice, LFE2-50E-VID-EV Datasheet - Page 100

• Manufacturer Part Number: LFE2-50E-VID-EV
• Description: Development Software LatticeECP2 Video Dev Kit
• Manufacturer: Lattice

Specifications of LFE2-50E-VID-EV

• Tool Type: Development Software Kit
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-15. sysCONFIG Parallel Port Write Cycle
Figure 3-16. sysCONFIG Slave Serial Port Timing
Figure 3-17. Power-On-Reset (POR) Timing
CCLK (input)
WRITEN
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
V
1. Time taken from V
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
CCLK
CS1N
BUSY
D[0:7]
CC
CSN
DOUT
/V
CFG[2:0]
DIN
CCAUX
DONE
CCLK
INITN
1
1
2
3
CC
or V
t
SUCBDI
CCAUX
, whichever is the last to reach its V
t
t
SUWD
SUCS
Byte 0
t
SUSCDI
t
ICFG
t
SUCFG
t
BSCL
3-48
Byte 1
t
SSCL
t
HCBDI
t
VMC
Valid
Byte 2
MIN
t
DCB
DC and Switching Characteristics
.
LatticeECP2/M Family Data Sheet
t
t
HCFG
BSCYC
t
t
BSCH
CODO
t
SSCH
Byte n
t
HSCDI
t
HCS
t
HWD