LFE2-50E-VID-EV Lattice, LFE2-50E-VID-EV Datasheet - Page 19

• Manufacturer Part Number: LFE2-50E-VID-EV
• Description: Development Software LatticeECP2 Video Dev Kit
• Manufacturer: Lattice

Specifications of LFE2-50E-VID-EV

• Tool Type: Development Software Kit
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices
have four secondary clocks (SC0 to SC3) which are distrubed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-15. Secondary Clock Regions ECP2-50
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
Region 4
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
2-16
I/O Bank 1
I/O Bank 4
Region 5
Region 6
Region 7
Region 8
LatticeECP2/M Family Data Sheet
Vertical Routing
Channel Regional
Boundary
DSP Row
Regional
Boundary
DSP Row
Regional
Boundary
EBR Row
Regional
Boundary
Architecture