LFE2-50E-VID-EV Lattice, LFE2-50E-VID-EV Datasheet - Page 17
LFE2-50E-VID-EV
Manufacturer Part Number
LFE2-50E-VID-EV
Description
Development Software LatticeECP2 Video Dev Kit
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2-50E-VID-EV
Tool Type
Development Software Kit
Core Architecture
CPLD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12.
Figure 2-12. Edge Clock Sources
From Routing
From Routing
Sources for left edge clocks
Input
Input
DLL
PLL
Clock
Clock
Input
Input
DLLDELA
GPLL
DLL
Routing
Routing
From
From
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Clock Input
Clock Input
2-14
Clock Input
Clock Input
Routing
Routing
From
From
Sources for top
LatticeECP2/M Family Data Sheet
bottom edge
Sources for
edge clocks
clocks
Sources for right edge clocks
GPLL
DLL
DLLDELA
Architecture
From Routing
From Routing
Clock
Clock
Input
Input
Input
Input
DLL
PLL
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