PAC-SYSTEMCLK5520 Lattice, PAC-SYSTEMCLK5520 Datasheet - Page 20

• Manufacturer Part Number: PAC-SYSTEMCLK5520
• Description: Development Software ispCLK5520 Design Sys
• Manufacturer: Lattice

Specifications of PAC-SYSTEMCLK5520

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 14. Flipping Polarity to Edge Align Two Outputs
For V-divider combinations in which one or more of the V-dividers is configured to a value that is not divisible by 4
(e.g. 6), there exists the possibility that neither rising nor falling edges may align. For example, when V-divider val-
ues of 6 and 12 are chosen, the two resulting outputs will have no edge alignment, as shown in Figure 15. Note
that because the offset is 2 VCO periods in this case, it is not possible to use the skew adjustment feature to force
any of the edges into perfect alignment as the skew control units provide a maximum delay of 1.875 VCO periods.
Figure 15. Timing Relationship Between V-divider Values of 6 and 12
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the output of the M divider
is routed directly to the inputs of the V dividers. In PLL_BYPASS mode, the nominal values of the V dividers are
halved, so that they provide division ratios ranging from 1 to 32. The divide-by-1 setting, however, is invalid and will
produce undefined results. The output frequency for a given V divider (f
Please note that PLL_BYPASS mode is provided primarily for testing purposes. When PLL_BYPASS mode is
enabled, features such as lock detect and skew generation are unavailable.
Reference Inputs
The ispClock5500 provides sets of configurable, internally-terminated inputs for clock reference signals. In normal
operation, the clock reference input (REFA) is connected to the system clock from which the output signals are to
be derived.
The ispClock5510 provides one input signal pair for reference input, while the ispClock5520 provides two input
pairs for reference signals. To select between reference inputs, the ispClock5520 provides a CMOS-compatible dig-
ital input called REFSEL. Table 4 shows the behavior of this control input:
Table 4. REFSEL Operation for ispClock5520
Polarity
Output
output
Invert
of
/8
/12
/16
/16
/6
/8
/8
Leading edges align
REFSEL
0
1
f
k
=
Trailing edges align
Selected Input Pair
20
M x V
Never Align
f
ref
Edges
REFA+/-
REFB+/-
k
k
) will be determined by
ispClock5500 Family Data Sheet
AFTER
BEFORE
(2)