PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 5

MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD

PAC-POWR607-EV

Manufacturer Part Number
PAC-POWR607-EV
Description
MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
Manufacturer
Lattice
Series
ispPAC®r
Datasheets

Specifications of PAC-POWR607-EV

Processor To Be Evaluated
ispPAC-POWR607
Interface Type
JTAG
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.96 V
Core Architecture
CPLD
Main Purpose
Power Management, Power Supply Supervisor/Tracker/Sequencer
Embedded
Yes, Other
Utilized Ic / Part
ispPAC-POWR607
Primary Attributes
-
Secondary Attributes
4.5 ~ 9 V Supply
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ispPAC-POWR607
Lattice Semiconductor
Evaluation Board User’s Guide
Appendix A. Schematics
The following figures comprise the schematics for the ispPAC-POWR607 evaluation board. Figure 3 shows the
device schematic and JTAG interface, while Figure 4 shows the on-board power-supply circuitry and the LED dis-
play.
Figure 3. ispPAC-POWR607 Device Schematic
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