ST7263-EMU2 STMicroelectronics, ST7263-EMU2 Datasheet - Page 23

• Manufacturer Part Number: ST7263-EMU2
• Description: MCU, MPU & DSP Development Tools ST7 Emulator Board
• Manufacturer: STMicroelectronics

Specifications of ST7263-EMU2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2 POWER SAVING MODES
4.2.1 Introduction
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 (f
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
4.2.2 HALT mode
The HALT mode is the MCU lowest power con-
sumption mode. The HALT mode is entered by ex-
ecuting the HALT instruction. The internal oscilla-
tor is then turned off, causing all internal process-
ing to be stopped, including the operation of the
on-chip peripherals.
When entering HALT mode, the I bit in the Condi-
tion Code Register is cleared. Thus, any of the ex-
ternal interrupts (ITi or USB end suspend mode),
are allowed and if an interrupt occurs, the CPU
clock becomes active.
The MCU can exit HALT mode on reception of ei-
ther an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillator is then turned on and a stabi-
lization time is provided before releasing CPU op-
eration. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
CPU
).
Figure 16. HALT Mode Flow Chart
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
N
INTERRUPT*
EXTERNAL
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
OR SERVICE INTERRUPT
I-BIT
FETCH RESET VECTOR
N
4096 CPU CLOCK
CYCLES DELAY
HALT INSTRUCTION
RESET
Y
OFF
OFF
OFF
CLEARED
ON
ON
ON
SET
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