ST7263-EMU2 STMicroelectronics, ST7263-EMU2 Datasheet - Page 42

• Manufacturer Part Number: ST7263-EMU2
• Description: MCU, MPU & DSP Development Tools ST7 Emulator Board
• Manufacturer: STMicroelectronics

Specifications of ST7263-EMU2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7263
16-BIT TIMER (Cont’d)
5.4.3.4 Output Compare
In this section, the index, i , may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
Timing resolution is one count of the free running
counter: (
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OC i E bit if an output is needed then the
– Select the timer clock (CC[1:0]) (see
And select the following in the CR1 register:
– Select the OLVL i bit to applied to the OCMP i pins
– Set the OCIE bit to generate an interrupt if it is
When a match is found between OCRi register
and CR register:
– OCF i bit is set.
42/109
OCMP i pin is dedicated to the output compare i
signal.
after the match occurs.
needed.
– Assigns pins with a programmable value if the
– Sets a flag in the status register
– Generates an interrupt if enabled
OC i R
OCIE bit is set
f
CPU/
CC[1:0]
i
R value to 8000h.
MS Byte
OC i HR
).
LS Byte
OC i LR
Table
1).
– The OCMP i pin takes OLVL i bit value (OCMP i
– A timer interrupt is generated if the OCIE bit is
The OC
ing application can be calculated using the follow-
ing formula:
Where:
f
PRESC
If the timer clock is an external clock, the formula
is:
Where:
f
Clearing the output compare interrupt request (i.e.
clearing the OCF i bit) is done by:
1. Reading the SR register while the OCF i bit is
2. An access (read or write) to the OC i LR register.
The following procedure is recommended to pre-
vent the OCF i bit from being set between the time
it is read and the write to the OC
– Write to the OC i HR register (further compares
– Read the SR register (first step of the clearance
– Write to the OC i LR register (enables the output
CPU
EXT
t
t
pin latch is forced low during reset).
set in the CR2 register and the I bit is cleared in
the CC register (CC).
are inhibited).
of the OCF i bit, which may be already set).
compare function and clears the OCF i bit).
set.
i
R register value required for a specific tim-
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 de-
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
pending on CC[1:0] bits, see
OC i R =
OC i R =
t
*
PRESC
t
f
EXT
*
f
CPU
i
R register:
Table
1)