AD12401-326JWS Analog Devices Inc, AD12401-326JWS Datasheet

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... SFDR. The product operates 400 MSPS conversion rate with outstanding dynamic performance in wideband carrier systems. The AD12401 requires a 3.7 V analog supply and 3.3 V and 1.5 V digital supplies, and provides a flexible ENCODE signal that can be differential or single ended. No external reference is required. The AD12401 package style is an enclosed 2.9" ...

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... Initial Version Time-Interleaving ADCs........................................................... 18 Analog Input ............................................................................... 18 Clock Input.................................................................................. 18 Digital Outputs ........................................................................... 19 Power Supplies............................................................................ 19 Start-Up and RESET .................................................................. 19 DR_EN......................................................................................... 19 Overrange.................................................................................... 19 Gain Select................................................................................... 20 Thermal Considerations............................................................ 20 Package Integrity/Mounting Guidelines ................................. 20 AD12401 Evaluation Kit ........................................................... 21 Data Outputs............................................................................... 21 Layout Guidelines........................................................................... 26 PCB Interface .............................................................................. 26 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 Rev Page ...

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... AD12401 Max Unit Bits +12 LSB +10 %FS LSB LSB %/° MHz 3.8 V 3.4 V 1.55 V 1.2 A 500 mA 1 Ω p-p Ω ...

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... Full IV 5.0 Full IV 396 60°C V 60°C V Rev Page AD12401-xxxKWS AD12401-xxxJWS Typ Max Min Typ 350 454 247 350 1.25 1.375 1.125 1.25 1.602 0.898 AD12401-400JWS Typ Max Min Typ 63.5 59.5 61 62.5 57.5 60.5 63.5 57 61.5 63 56.5 61 61.5 55.5 59.5 60 ...

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... Full IV Rev Page AD12401 AD12401-400JWS Typ Max Min Typ Max 3.9 3.9 8.7 8.7 0.3 0.3 0.3 0.3 11.2 11.2 2.5 2 2.8 2.8 2.3 2.3 0.4 0.4 AD12401-360KWS Min Typ Max 62 64 61.5 63 63.5 58.5 63 57.5 61 −75 10 160 5.6 Unit ns ns ...

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... Full I 60 Full I 60 Full I 60 60°C V 60°C V Rev Page AD12401-360KWS Min Typ Max 356 360 364 1.38 1.38 4.5 8.7 0.3 0.3 11.5 2 3.1 2.3 0.4 AD12401-326JWS Typ Max Min Typ Max 63.5 59.5 61 63.5 57 61.5 63 56.5 61 61.5 55.5 59 ...

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... V 60°C V 60°C V Full IV Full IV 29 Full IV 60°C V 60°C V /2. S required for data to emerge. PD Rev Page AD12401 AD12401-326JWS Typ Max Min Typ Max 140 10 140 6.2 326 329 323 326 329 1.53 1.53 1.53 1.53 5.0 5.0 8.7 8 ...

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... AD12401 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter VA to AGND VC to DGND VD to DGND Analog Input Voltage Analog Input Power ENCODE Input Voltage ENCODE Input Power Logic Inputs Storage Temperature Range, Ambient Operating Temperature Range EXPLANATION OF TEST LEVELS Table 6. Level Description I 100% production tested. ...

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... THE 50% POINT AND APPLY THE SAME TIMING INFORMATION. 3. THE DR_EN PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES. THE DR_EN PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12401. IF APPLIED ASYNCHRONOUSLY, DR_EN MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION. ...

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... AD12401 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AIN ENC ENC TOP VIEW JOHNSON SMA-50 Ω CONNECT NO. 142-0711-821 2-56 STUDS 4⋅ END VIEW SAMTEC CONNECTOR QTE-060-01-L-D-A-K-TR ENC ENC AIN BOTTOM VIEW NOTE: 1. FOR MATING CONNECTOR, USE SAMTEC, INC. PART NO. QSE-60-01-L-D-A-K. INTEGRAL GROUND PLANE CONNECTIONS. ...

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... Channel A Data Bit 7. True output bit. 64 DA6 Channel A Data Bit 6. True output bit. 65 DA5 Channel A Data Bit 5. Complement output bit. 66 DA4 Channel A Data Bit 4. Complement output bit. 67 DA5 Channel A Data Bit 5. True output bit. 68 DA4 Channel A Data Bit 4. True output bit. Rev Page AD12401 ...

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... AD12401 Pin No. Mnemonic Description 69 DA3 Channel A Data Bit 3. Complement output bit. 70 DA2 Channel A Data Bit 2. Complement output bit. 71 DA3 Channel A Data Bit 3. True output bit. 72 DA2 Channel A Data Bit 2. True output bit. 73 DA1 Channel A Data Bit 1. Complement output bit. 74 DA0 Channel A Data Bit 0. Complement output bit. DA0 is LSB. ...

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... ENCODE (or zero crossing of a single-ended ENCODE). Pipeline Latency The number of clock cycles the output data lags the correspond- ing clock cycle. Power Supply Rejection Ratio (PSRR) The ratio of power supply voltage change to the resulting ADC output voltage change. Rev Page AD12401 2 rms = 10 log ((V Full-Scale )/(|Z Full-Scale INPUT ...

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... AD12401 Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc and image spur. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc ...

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... FREQUENCY (MHz) Figure 11. Two-Tone Intermodulation Distortion (70.1 MHz and 73.1 MHz 400 MSPS Image Spur Interleaved Offset Spur AD12401 160 180 200 160 180 200 160 180 200 ...

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... AD12401 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 100 120 FREQUENCY (MHz) Figure 12. Two-Tone Intermodulation Distortion (172.1 MHz and 175.1 MHz 400 MSPS), SFDR = 70 dBc Image Spur Interleaved Offset Spur 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 – ...

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... ANALOG INPUT FREQUENCY Figure 18. Low Frequency Gain Flatness Rev Page AD12401 ...

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... N CLOCK INPUT 6 The AD12401 requires a 400 MSPS ENCODE that is divided by 2 and distributed to each ADC channel, 180° out of phase from each other. Internal ac-coupling and bias networks provide the framework for flexible clock input requirements that include ...

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... EMI. For exam 10MHz IN ple, a system goal dynamic range performance on the AD12401 requires noise currents that are less than 4.5 μA and A = 65MHz IN noise voltages of less than 225 μV in the analog input path. STARTUP AND RESET ...

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... AD12401 GAIN SELECT The AD12401 is graded out for the gain mode and should be ordered accordingly: the AD12401-xxxKWS is calibrated in the low gain mode, and the AD12401-xxxJWS is calibrated in the high gain mode. Performance is not guaranteed if either grade is used in the wrong gain mode. The high gain mode sets the analog input voltage to approximately 1 ...

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... AD12401 without the digital postprocessing. RESET The AD12401’s FPGA configuration is stored in an EEPROM and loaded into the FPGA when power is applied to the AD12401. The RESET switch, SW1 (active low), allows the user to reload the FPGA in case of a low voltage condition or a power supply glitch ...

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... DGND Device Capacitors Capacitors Resistor 2-Pin Header/Jumper 80-Pin Dual Connector Assembly Switch Push Button SPST 4-Pin Header Power Connecters 60-Pin Dual-Socket Assembly AD12401 Interface Board GS08054 R8 4.02kΩ 3.3VC SPARE1 SPARE1 AFB PASS SPARE2 SPARE2 R9 4.02kΩ 3.3VC H/L_GAIN H/L_GAIN R10 4.02kΩ ...

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... DA0 DA0 PASS DNC DA10 DA10 DA8 DA8 OR DA6 OR DA6 DA4 DA4 DA2 DA2 DGND DA0 DA0 DRA DRA DNC WP 3.3VC DNC DNC DNC +VA Figure 25. Evaluation Board Rev Page AD12401 P2:C P2 DRB 44 4 DRB DB11 48 8 DB11 49 9 DB10 50 10 DB10 51 ...

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... AD12401 Figure 26. Power Plane 1 Figure 27. Power Plane 2 Figure 28. First Ground Plane Figure 29. Second Ground Plane Figure 30. Top Side Copper Figure 31. Bottom Side Copper Rev Page ...

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... Figure 32. Top Mask Figure 33. Top Silkscreen Figure 34. Bottom Silkscreen Figure 35. Evaluation Adapter Board, Top Silkscreen Figure 36. Evaluation Adapter Board, Analog and Digital Layers Figure 37. Evaluation Adapter Board, Bottom Silkscreen Rev Page AD12401 ...

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... EMI in the system. One critical consideration is that a 12-bit perform- ance requirement (–74 dBc) requires keeping conducted EMI currents (referenced to the input of the AD12401) below 4.5 μA. All the characterization and testing of the AD12401 is performed using a system that isolated these ground planes. ...

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... R.0470[R1.19] 6× Figure 38. Top View of Interface PCB Assembly Rev Page 1.184 [30.0673] 1.025 [26.0164] 2× DATUM = CENTER OF CONNECTOR .000 [.0000] 1.025 [26.0164] 2× 1.184 [30.0673] AD12401 ...

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... JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821 0.700 MAX 0.175 TYP 2.060 2.040 0.505 TYP 2⋅ ORDERING GUIDE Model Temperature Range AD12401-326KWS 0°C to 60°C (Case) AD12401-326JWS 0°C to 60°C (Case) AD12401-360KWS 0°C to 60°C (Case) AD12401-400KWS 0°C to 60°C (Case) AD12401-400JWS 0°C to 60°C (Case) 1 AD12401/KIT 1 The encode rate and gain mode must be selected when ordering the AD12401/KIT. The standard AD12401/KIT is configured for low gain mode at 400 MSPS. © ...