AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 10

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. 28-lead TSSOP Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
MCLK1
MCLK2
SCLK
CS
P3
P2
P1/REFIN2(+)
P0/REFIN2(−)
NC
AINCOM
AIN1
AIN2
AIN3
Description
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a
crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin
can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information transmitted to or from the ADC in smaller batches of data.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV
AGND.
Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV
AGND.
Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced
between AV
REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie
anywhere between AV
the part functions with a reference from 1 V to AV
Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced
between AV
REFIN2(−). This reference input can lie anywhere between AGND and AV
No Connect. Tie this pin to AGND.
Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential
operation.
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN2 or as a pseudo differential input when used with AINCOM.
Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN1 or as a pseudo differential input when used with AINCOM.
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudo differential input when used with AINCOM.
DD
DD
and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as
and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as
P1/REFIN2(+)
P0/REFIN2(–)
Figure 5. 28-lead TSSOP Pin Configuration
DD
AINCOM
MCLK1
MCLK2
SCLK
and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AV
AIN1
AIN2
AIN3
AIN4
NC
CS
P3
P2
10
12
13
14
11
1
4
Rev. B | Page 10 of 56
2
3
5
6
7
8
9
NC = NO CONNECT
(Not to Scale)
AD7193
TOP VIEW
27
26
24
22
20
19
18
17
16
15
28
25
23
21
DIN
DOUT/RDY
SYNC
DV
AV
DGND
AGND
BPDSW
REFIN1(–)
REFIN1(+)
AIN8
AIN7
AIN6
AIN5
DD
DD
DD
.
DD
− 1 V.
DD
DD
and
and
DD
, but